Communications control bus and apparatus for controlling multiple electronic hardware devices

ABSTRACT

Disclosed is a communications control bus. The bus comprises an IMB slave CPU, at least two registers, and a three bit data connector, which connects the two registers. The connector permits transmission of a three bit data signal between the two registers. A network interconnects the two registers and the IMB slave CPU.

FIELD OF THE INVENTION

The present invention concerns a communications control bus, and moreparticularly to a control bus for controlling multiple electronichardware devices.

BACKGROUND OF THE INVENTION

Building automation systems are well known and widely used in residencesand industrial environments. Typically, multiple systems and devicessuch as climate control, lighting, temperature control and the like arecontrolled by a controller located remotely from the systems to becontrolled.

Power Line Carrier (PLC) technology or protocol is one technology thathas existed for over twenty years and uses a command signal transmittedover the existing 120 volt home electrical wiring system. However, somePLC systems are subject to interference from other electrical systems,creating such inconveniences as unanswered or false commands.

Wireless technology using radio frequencies (RF) are sometimes used innewer home constructions, but more typically is used in older homes forexpanding existing hardwired systems. Typically, a command signal istransmitted by radio waves to a central controller. However, thistopology requires additional hardware and space to accommodate thecentral controller and is usually a closed platform, which prevents theuser from modifying certain logic sequences or adding specific hardwarefunctionality.

Low voltage hardwired systems have been used for over forty years tocreate a communications network within the home. This technology usescommunications over a data path over wires placed in the walls of thehouse before they are covered with plaster. Each control device includesa copper wire connecting it to a main controller. Furthermore, with theadvent of computer controlled systems and controlling software, theremote control of the multiple systems and devices would appear to bestraightforward. However, to install such systems in buildings,typically the interior of the buildings have to be re-modeled. Inresidential environment, such as homes, remodeling can be prohibitivelyexpensive and typically requires structural modifications to walls andexisting wiring to install additional complex wiring to accommodate suchcontroller systems.

A number of examples have been disclosed which address the aforesaidproblems. In U.S. Pat. No. 6,980,080, issued on Dec. 27, 2005 toChristensen et al., a wireless home automation system is disclosed inwhich multiple controllers control a variety of functions using atwo-way communication with a number of devices such as lighting, burglaralarms, thermostats and the like. This system appears to rely on learntinformation between the controllers, which is stored in a memory foreach controller. In U.S. Pat. No. 6,967,565 issued on Nov. 22, 2005 toLingemann, a building automation system is disclosed which uses multipleuser interface units with touch screens, power drivers and a controller.All of these are connected to a common trunk conductor. From the userinterface unit, multiple electrical devices in a building may becontrolled by the units and wireless remote controls. In U.S. Pat. No.6,865,596, issued on Mar. 8, 2005 to Barber et al., a master controllerin a control area network system is disclosed, within a larger controlarea network, and which may have a number of devices connected to it.The master controller has a device manager which provides a so-called“virtual device”. U.S. Pat. No. 6,813,525, issued on Nov. 2, 2004 toReid et at discloses a programmable control system which includes acontrol module having one or more inputs to which a sensor device can beconnected. Also included is an external actuator device which can beused for manual override and status feedback. This system appears torely on a learning mode and a memory to store characteristics of theexternal sensor. In U.S. Pat. No. 6,192,282, issued on Feb. 20, 2001 toSmith et al., a building automation system, which is modular in designis disclosed and which minimizes the amount of instruction needed tocontrol a building system. The system appears to operate by translatingcontrol instructions in one control protocol to control instructions ina second control protocol. In U.S. Pat. No. 5,706,191, issued on Jan. 6,1998 to Bassett et al., a method for bringing an appliance and/or amechanical/electrical system of a residence into communication withanother is disclosed. To achieve this, each appliance is provided withan appliance interface module apparatus. U.S. Pat. No. 5,557,545, issuedon Sep. 17, 1996 to Loffel et al., discloses an automatic control for apower plant with a number of interacting plant components having anautomation system which is shared by the plant components, and withautomation devices executing various functions. The automation devicesare connected to each other and to a master control unit though a databus which transmits plant relevant data. U.S. Pat. No. 5,289,365, issuedon Feb. 23, 1994 to Caldwell et al., discloses a module electricalcontrol system for controlling office equipment. The system includes anumber of control modules which are interconnected with an input modulevia a bus assembly. A keypad appears to generate an input signal, anoutput port to which the system bus assembly is connected and a circuitwhich is responsive to the input signal for supplying a command signalto the output port. The system bus assembly includes at least two signalchannels, one of which is selectively supplied with a switched lowvoltage signal, the other being selectively supplied with a data signal.In U.S. Pat. No. 5,128,855, issued on Jul. 7, 1992 to Hilber et al., asystem for controlling an operating installation of a building'sautomation system is disclosed. The system comprises a control modulewhich serves as a master transmitter-receiver and a function module,which serves as a slave transmitter. A bus connection includes a busrail which connects the control module and the function module totransmit addresses and data, and operating voltages. In US patentapplication no. 2005/0125083, published on Jun. 9, 2005 to Kilco, aserver-based system for providing a substantially automated operationand control of a number of functions within a premises, such asresidence, is disclosed.

The aforesaid designs suffer from a number of significant drawbacks.None of the designs appear to be retrofittable into an existinghousehold wiring network using existing household electrical boxes. Thedesigns appear to be complex and may be prohibitively expensive toinstall into industrial, commercial or household environments. Some ofthe designs appear to be server based, which may not be practical forhousehold systems control. In one example, each appliance to becontrolled appears to be provided with an interface module, whichpresumably would mean that each household appliance would have to bewired up to its AIM. This may be prohibitively expensive and wouldrequire modifying existing appliances.

Thus, there is a need for an improved controller for remotelycontrolling multiple electronic hardware devices, which is simple toinstall and modular with straightforward expandability.

SUMMARY OF THE INVENTION

I have made a surprising and unexpected discovery that multipleelectronic hardware devices can be remotely controlled from a singlelocation. This is achieved by using a modified control bus, the designof which allows a simple “plug in” of expandable modules whichquadruples the available circuitry from a single location. The bus islocated in a module, which can be retrofitted into an existing householdelectrical box, such as found in light switches, thereby significantlyreducing, or essentially eliminating, the need for remodeling anexisting wiring system in a house. Advantageously, this reduces the costof remodeling and disruption of the household.

Accordingly in one aspect, there is provided a communications controlbus, the bus comprising:

-   -   a) an IMB slave CPU;    -   b) at least two registers;    -   c) a first three bit data connector for connecting the at least        two registers, the connector permitting transmission of a three        bit data signal between the at least two registers; and    -   d) a network interconnecting the at least two registers and the        IMB slave CPU.

Typically, the at least two registers comprise:

-   -   a) a first control register; and    -   b) a first data register;    -   e) the network interconnecting the first control register and        the first data register, the network being configured such that        in response to a first at least 8 bit data signal being received        at the first control register, a first 3 bit disable command        signal is transmitted by the first control register to the first        data register.

Typically, the at least two registers further comprise:

-   -   a) a second control register;    -   b) a second data register;    -   c) a third control register;    -   d) a third data register;    -   e) a fourth control register; and    -   f) a fourth data register;    -   g) the network being configured such in response to second,        third, and fourth at least 8 bit data signals being received        respectively at the second, third and fourth control registers,        a second, third and fourth 3 bit disable command signal is        transmitted to the respective second, third and fourth data        registers.

In one example, the network is configured such in response to fifth,sixth, seventh and eighth at least 8 bit data signals being receivedrespectively at the first, second, third and fourth control registers, afifth, sixth, seventh, and eighth 3 bit load command signal istransmitted to the respective first, second, third and fourth dataregisters so that each data register is permitted to receive at least 8bits of data. The network is configured such in response to ninth,tenth, eleventh and twelfth at least 8 bit data signals being receivedrespectively at the first, second, third and fourth control registers, afifth, sixth, seventh and eighth 3 bit disable command signal istransmitted to the respective first, second, third and fourth dataregisters. The network is configured such in response to a 3 bit unloadcommand signal is transmitted to the respective first, second, third andfourth data registers from the respective first, second, third andfourth control registers, the at least 8 bits of data stored in the dataregisters is transmitted to the IMB slave CPU. The first controlregister is paired with the first data register; the second controlregister is paired with the second data register; the third controlregister is paired with the third data register; and the fourth controlregister is paired with the fourth data register. The at least tworegisters are connected by a 3 bit command signal. In one example, afirst 32 bit stream of data is received by the first, second, third andfourth control registers. A second 32 bit stream of data is received bythe first, second, third and fourth data registers. The second 32 bitstream of data is transmitted from the fourth data register to the IMBslave CPU. An SL1 signal wire connects the IMB slave CPU to the firstcontrol register. An SL2 signal wire connects the IMB slave CPU to thefirst data register. A first clock signal wire interconnects the first,second, third and fourth control registers to the IMB slave CPU. Anenable signal wire interconnects the first, second, third and fourthcontrol registers to the IMB slave CPU. A second clock signal wireconnects the first, second, third and fourth data registers to the IMBslave CPU. A DQA feedback wire connects the fourth data register to theIMB slave CPU.

In one example, each control register includes at least one input/outputpin and each data register includes at least one input/output pin. Atleast three wires interconnect each paired control register and dataregister. Each control register transmits a 3 bit command signal to eachdata register located adjacent thereto. The at least two registers andthe first three bit data connector comprise a 13 bit bus. The 13 bit busincludes an eight bit bi-directional data register and five mostsignificant output bits of an adjacent control register. The first threebit data connector issues a command to the adjacent control register. Atleast one ACM connector is connected to each pair of control registersand data registers. The bus includes four ACM connectors. The busfurther comprising a HUS and a MUC. Each IMB includes at least fourMUCs.

Accordingly in another aspect, there is provided a modular apparatus forcontrolling multiple electronic hardware devices, the apparatuscomprising:

-   -   a) at least one intelligent master base for use with an        electrical circuit;    -   b) a first communications control bus, as described above,        located in the intelligent master base; and    -   c) at least one adaptable cube module connected to the        intelligent master base, the communications control bus being        adapted to allow the number of adaptable cube modules to be        increased in multiples of four.

In one example, an intelligent slave base is connected to theintelligent master base. A second communications control bus is locatedin the intelligent slave base. The intelligent master base and theadaptable cube module are sized and shaped for location in an electricalbox. A smart plate is connected to the adaptable cube module. A smartplate is connected to the intelligent slave base. A smart plate isconnected to the intelligent master base. A slim slave base module isconnected to the intelligent master base. A slim slave base module isconnected to the intelligent slave base.

In one example, the intelligent master base comprises:

-   -   a) an IMB master CPU;    -   b) an IMB slave CPU electrically connected to the IMB master CPU        via an I²C standard;    -   c) at least two adaptable cube module connectors for receiving        the adaptable cube modules;    -   d) a first HUS bus interconnecting the at least two adaptable        cube module connectors to the IMB slave CPU;    -   e) a circuit for remotely controlling the multiple electronic        hardware devices, the circuit being connected to the IMB slave        CPU; and    -   f) a power supply for powering the circuit, the IMB master CPU,        and the IMB slave CPU, the power supply being connected to an        electrical wiring network.

The IMB slave CPU is a PIC micro-controller or DSC/DSP processors. Eachadaptable cube module connector is at least a 28 pin header. Theintelligent master base further includes an RF transceiver chip having amesh topology stack, the stack communicating information in the formatof the SPTN communications protocol.

In another example, the intelligent slave base further comprises:

-   -   a) an ISB master CPU;    -   b) at least two adaptable cube module connectors for receiving        the adaptable cube modules;    -   c) a second communications control bus, as described above,        located in the intelligent slave base; and    -   d) a second HUS bus interconnecting the at least two adaptable        cube module connectors to the ISB master CPU; and    -   e) a power supply for powering the ISB master CPU, the power        supply being connected to the IMB.

In another example, each adaptable cube module comprises:

-   -   a) an adaptable cube module connector for receiving the        intelligent master base;    -   b) a conductive circuit having an eight bit bus portion, and        first and second routes;    -   c) an 8 bit bus control buffer connected to the second route;        and    -   d) a plurality of resistors connected to the first route, the        resistors defining an address of the adaptable cube module, the        conductive circuit communicating data from the intelligent        master base to the resistors.

The adaptable cube module connector includes a plurality of connectionsfor use with HUS services. The conductive circuit further comprises abuffer latch control connected to an output of a control register. Theapparatus further comprises a smart plate cover interface. The smartplate cover interface and the adaptable cube module may be one-piece.The resistors are parallel pull up or pull down resistors. Theintelligent slave base and the intelligent master base are connected bya base-expansion connector. The base expansion connector comprises anI²C standard. The smart plate includes a smoke detector, at least oneinfra red proximity detector, at least one motion detector, at least oneGFI (Ground fault interruption), at least one Arc detection, or at leastone lighting dimmer circuit. The intelligent master base and theadaptable cube module are located in an 1104, 4×4 or 4/11/16, 6×6, 8×8,10×10, 12×12, 16×16 or 24×24 electrical box. The slim slave base modulecomprises a PC board for communicating conductive traces between baseexpansion connectors, the board having located therein a plurality ofholes through which power conductors pass independent of the conductivetraces. Alternatively, the slim slave base module comprises a PC boardfor communicating conductive traces between base expansion connectors,the board having a plurality of housing terminal screws for connectingto the electrical wiring system.

According to another aspect, there is provided an intelligent masterbase comprising:

-   -   a) an IMB master CPU;    -   b) an IMB slave CPU electrically connected to the IMB master CPU        via an I²C standard;    -   c) four adaptable cube module connectors for receiving        respectively four adaptable cube modules;    -   d) a HUS bus interconnecting the adaptable cube module        connectors to the IMB slave CPU;    -   e) a circuit for remotely the controlling the multiple        electronic hardware devices, the circuit being connected to the        IMB slave CPU; and    -   f) a power supply for powering the circuit, the IMB master CPU,        and the IMB slave CPU, the power supply being connected to an        electrical wiring network.

In one example, the IMB slave CPU is a PIC micro-controller or DSC/DSPprocessors.

Each adaptable cube module connector is at least a 28 pin header. Theintelligent master base further includes an RF transceiver chip having amesh topology stack, the stack communicating information in the formatof the SPTN communications protocol.

According to yet another aspect, there is provided an intelligent slavebase comprising:

-   -   a) an ISB master CPU;    -   b) four cube module connectors for receiving respectively four        adaptable cube modules;    -   c) a communications control bus, as described above, located in        the intelligent slave base; and    -   d) a HUS bus interconnecting the adaptable cube module        connectors to the ISB master CPU; and    -   d) a power supply for powering the ISB master CPU, the power        supply being connectable to an intelligent master base.

According to still another aspect, there is provided an adaptable cubemodule comprising:

-   -   a) an adaptable cube module connector for receiving an        intelligent master base;    -   b) a conductive circuit having an eight bit bus portion, and        first and second routes;    -   c) an 8 bit bus control buffer connected to the second route;        and    -   d) a plurality of resistors connected to the first route, the        resistors defining an address of the adaptable cube module, the        conductive circuit communicating data from the intelligent        master base to the resistors.

In one example, the adaptable cube module connector includes a pluralityof connections for use with HUS services. The conductive circuit furthercomprises a buffer latch control connected to an output of a controlregister. The resistors are parallel pull up or pull down resistors.

According to another aspect, there is provided a slim slave base modulecomprising: a PC board for communicating conductive traces between baseexpansion connectors, the board having located therein a plurality ofholes through which power conductors pass independent of the conductivetraces.

According to an alternative aspect, there is provided a slim slave basemodule comprising a PC board for communicating conductive traces betweenbase expansion connectors, the board having a plurality of housingterminal screws for connecting to the electrical wiring system.

In one example of the above, the smart plate includes features selectedfrom the group consisting of: a graphical color touch screen, a batterycharger, proximity sensors, a long range motion sensor, a thermostat alux meter (TAOS technology, a smoke detector, doorbell buzzer system,video camera images, a humidistat an intercom system an intrusionsystem, a camera, programmable control function blocks, a permanentor/and detachable nightlight, virtual switches/dimmers, telephone andsmart tagging systems, displays readings associated to theestablishments hot water tank(s) which determine the amount of hot wateravailable per tank.

In yet another example of the above, the electrical box includes any acombination of one or more hardware devices selected from the groupconsisting of: IMB, ISB, MUCX's, RF communications in the IMB, lightingdimmer circuits, connectivity for a graphical color touch screen, a longrange motion detector, thermostat, a lux meter (TAOS technology), smokedetector, doorbell buzzer button, humidistat, intercom, camera, batterycharger, GFI (Ground fault interruption), arc detector, single or duplexreceptacles, motion sensor, single/double pole button switches, AC/DCdiscrete low/high voltage input, AC/DC discrete low/high voltage output,DC analog voltage/current output, DC analog voltage/current input, CO₂sensor, RS232 RF links, DAC, ADC, on/off photocell, RS232, RF-RS-232,RS-422, RS-485, RF-RS-422, RF-RS-485, pulse width modulator output,buzzer, night light, power bar with electrical cord, witch/dimmerbuttons and battery charger.

Typically, the intelligent master base is cuboid, the intelligent slavebase is cuboid., and the adaptable cube module is cuboid.

According to yet another aspect, there is provided a one-piece apparatusfor controlling multiple electronic hardware devices, the apparatuscomprising:

-   -   a) an adaptable cube module connectable to an intelligent master        base; and    -   b) a smart plate cover interface connected to the adaptable cube        module.

In one example, the smart plate includes features selected from thegroup consisting of: a graphical color touch screen, a battery charger,proximity sensors, a long range motion sensor, a thermostat a lux meter(TAOS technology, a smoke detector, doorbell buzzer system, video cameraimages, a humidistat an intercom system an intrusion system, a camera,programmable control function blocks, a permanent or/and detachablenightlight, virtual switches/dimmers, telephone and smart taggingsystems, displays readings associated to the establishment's hot watertank(s) which determine the amount of hot water available per tank.

According to another aspect, there is provided a circuit for remotelycontrolling multiple hardware devices, the circuit comprising acommunications control bus, as described above.

According to yet another aspect, there is provided a method of remotelycontrolling multiple devices using a communications control bus, themethod comprising:

-   -   a) electrically interconnecting a first control register, a        first data register, and an IMB slave CPU; and    -   b) transmitting a three bit data disable signal from the first        control register to the first data register.

In one example, the method further comprising:

-   -   a) receiving a first at least 8 bit data signal at the first        control register; and    -   b) transmitting a first 3 bit disable signal from the first        control register to the first data register.

In another example, the method further comprising:

-   -   a) receiving second, third, and fourth at least 8 bit data        signals at respective second, third and fourth control        registers; and    -   b) transmitting a second, third and fourth 3 bit disable command        signal to the respective second, third and fourth data        registers.

In yet another example, the method further comprising:

-   -   a) receiving fifth, sixth, seventh and eighth at least 8 bit        data signals respectively at the first, second, third and fourth        control registers allowing its previous first, second, third and        fourth data bytes to be transferred to the fifth, sixth, seventh        and eighth control registers; and    -   b) transmitting a fifth, sixth, seventh, eighth, ninth, tenth,        eleventh and twelfth 3 bit load command signal to the respective        first, second, third, fourth, fifth, sixth, seventh and eighth        data registers so that each data register is permitted to        receive at least 8 bits of data.

In still another example, the method further comprising:

-   -   a) receiving ninth, tenth, eleventh and twelfth at least 8 bit        data signals respectively at the first, second, third and fourth        control registers allowing its previous fifth, sixth, seventh        and eighth data bytes to be transferred to the fifth, sixth,        seventh and eighth control registers; and    -   b) transmitting a thirteenth, fourteenth, fifteenth sixteenth,        seventeenth, eighteenth, nineteenth and twentieth, 3 bit disable        command signal to the respective first, second, third fourth,        fifth, sixth, seventh and eighth data registers.

In another example, the method further comprising:

-   -   a) transmitting a 3 bit unload command signal to the respective        first, second, third, fourth, fifth, sixth, seventh and eighth        data registers from the respective first, second, third, fourth,        fifth, sixth, seventh and eighth control registers; and    -   b) transmitting the at least 8 bits of data stored in the data        registers to the IMB slave CPU.

According to yet another aspect, there is provided a method ofcontrolling multiple electronic hardware devices using a touchless smartplate interface having a proximity detector, the smart plate interfacebeing connected to a modular apparatus, as described above, the methodcomprising: waving a hand at least once near the proximity detector tocontrol operation of a first electronic hardware device.

In one example, the method further comprising, after waving the hand atleast once, pausing the hand near the proximity detector so as tofurther control operation of the first electronic hardware device. Twoconsecutive hand wavings near the proximity detector operates a secondelectronic hardware device. Two consecutive having wavings followed by apause near the proximity detector further controls operation of thesecond hardware device. In another example, three consecutive handwavings near the proximity detector operates a third electronic hardwaredevice. Three consecutive hand wavings followed by a pause near theproximity detector further controls the third electronic hardwaredevice.

In another example, the hand is moved orthogonal to the proximitydetector so as to further control the electronic device. The hand ismoved orthogonal to the proximity detector so as to dim lights.

BRIEF DESCRIPTION OF THE FIGURES

Further aspects and advantages of the present invention will becomebetter understood with reference to the description in association withthe following Figures, wherein:

FIG. 1 is an exploded view of an embodiment of a modular apparatus;

FIG. 1A is an exploded view of an adaptable cube module (ACM) and asmart plate cover showing connectivity to an intelligent master base(IMB);

FIG. 2 is an exploded view of a modular apparatus showing location of aplate cover with an aperture;

FIG. 2A is a perspective view of a one-piece apparatus showing an ACMand a smart plate cover with connection to an intelligent master base;

FIG. 3 are photographs illustrating smart plate covers;

FIG. 3A is a diagram showing a modular IMB/ISB configuration;

FIG. 3B is a diagram showing a modular IMB/ISB/MUCX configuration andopen frame covers in combination with a smart plate cover;

FIG. 3C is a diagram showing a modular single/double gang IMB/ISBconfiguration with smart plate covers;

FIG. 3D is a diagram showing an unlimited modular assembly of multipleIMB/ISB/MUCX modules;

FIG. 3E is a comparative illustration showing the use of a smart platecover to control multiple devices from a single location;

FIG. 4 is a side view of the apparatus of FIG. 2 located in a domestic1104 electrical box;

FIG. 5 is an exploded view of a modular apparatus of FIG. 1 with a heatsink module and a plurality of other ACMs connected to an IMB and anintelligent slave base (ISB);

FIG. 6 is a perspective and a side view of an ACM apparatus showingstacked heat sinks used in a low power configuration;

FIG. 7 is an exploded view of an intelligent master base with a basicheat sink module in a vertically orientated domestic single gang 1104electrical box;

FIG. 8 is an exploded view of an alternative modular apparatus in a highpower configuration using stacked heat sink modules connected to a slimslave base (SSB) module and located in a 4×4 or 4/11/16 electrical box;

FIG. 8A is a detailed exploded view of an alternative modular apparatusin a high power configuration using stacked heat sink modules connectedto a slim slave base (SSB) module using conductive screws and located ina 4×4 or 4/11/16 electrical box;

FIG. 9 is a detailed side view of an alternative modular apparatusshowing an alternative location of stackable heat sinks;

FIG. 10 is a diagrammatic representation of an IMB and an ISB showingthe location of an IMB master CPU, an IMB slave CPU, an ISB master CPUand communication control buses;

FIG. 11 is a circuit diagram of an embodiment of a communicationscontrol bus (CD88 communication standard) located in an intelligentmaster base or an intelligent slave base (note that the “//” indicatestwo wires);

FIG. 12 illustrates serial bit manipulations in a first in first out(FIFO) operation using the circuit of FIG. 11;

FIG. 13 illustrates a loading operation of data registers using thecircuit of FIG. 11;

FIG. 14 illustrates an unloading operation of the data registers of FIG.13;

FIG. 15 illustrates a loading and writing to bus operation;

FIG. 16 is a diagram illustrating the identification circuit of an ACM;

FIG. 17 is an end view of an ACM connector identifying its pinouts;

FIG. 18 is an exploded perspective view of an alternative embodiment ofa modular apparatus showing stacked heat sink modules permitting theload wires to have access through the holes of the SSB module forconnections to the electrical network;

FIG. 19 is a circuit diagram showing the definition of a multipleuniversal communications (MUC);

FIG. 20 is a circuit diagram showing four MUCs;

FIG. 21 is a circuit diagram showing an additional eight 8 bit shiftregisters as part of a of a multiple universal communications extender(MUCX);

FIG. 22 is a general circuit diagram showing an intelligent master baseconnected to a MUCX providing 8 MUCS;

FIG. 23 is a diagram showing details of the components used in a MUC(which are CD88/HUS/PowerSupply connections) with corresponding signalsto the ACM connector.

FIG. 24 is a diagram illustrating the internal details of an IMB to ISBinstallation;

FIG. 24A is a diagram showing two ACMs connected to their respective ACMconnectors and illustrating the difference between where one ACMrequires hardware utility signals (HUS) and the other not requiring HUS.

FIG. 25 is a diagram showing the internal details of an IMB to MUCXinstallation;

FIG. 26 is a diagram showing the internal details of an ISB to MUCXinstallation;

FIG. 27 is a diagram showing the internal details of a combinational IMBor ISB/MUCX/MUCX/ISB or MUCX installation;

FIG. 28 is a schematic representation of a serial pillar to nodestransmission (SPNT);

FIG. 29 is a schematic representation of the SPNT in initial andoperational states;

FIG. 30 is a flow diagram showing system logic for processing many ACMssimultaneously and loading of registers;

FIG. 31 is a flow diagram showing system logic for processing one ACM ata time and loading of registers; and

FIG. 32 is a circuit diagram showing a circuit embedded in a MAX II CPLDand repeated 4 times so to achieve the complete CD88 circuit

DETAILED DESCRIPTION OF THE INVENTION

My discovery concerns a novel 13-bit bus, which communicates between anintelligent master base (IMB) and a number of adaptable cube modules(ACM). Each IMB includes four 13 bit ports, which can significantlyexpand the number of devices and systems that can be connected to theIMB and controlled via an interface. A user can easily control multiplehousehold systems from a single location using buttons or a touch screeninterface. To achieve this without using my 13 bit bus, fifty twodiscrete I/Os would be required eliminating the opportunity ofsimultaneously using any other on board MUC peripherals.

Modular Apparatus

Referring now to FIG. 1 a modular apparatus is shown generally at 10.Broadly speaking, the apparatus 10 comprises at least one IMB 12, and atleast one ACM 16A, which are connectable to the IMB 12. The apparatus 10optionally comprises an intelligent slave base (ISB) 14 and at least oneACM 16B connectable thereto. In the example shown, four ACMs 16A areconnected to the IMB 12, and four ACMs 16B are connected to the ISB 14.As will become apparent upon further reading of this description, thenumber of ACMs 16A or 16B can be expanded in multiples of four (as shownby the phantom lines in FIG. 1). Examples of ACM types 16A or 16Binclude, but are not limited to: single/double pole button switches;light dimming switches; single or duplex domestic 120 VAC/15 Areceptacles; single or duplex domestic 120 VAC/15 A receptacles withGFI/ACR detection capabilities; motion sensors; AC/DC discrete low/highvoltage input; AC/DC discrete low/high voltage output; DC analogvoltage/current output; DC analog voltage/current input; proximitysensor; RF link; DAC; ADC; opto module measuring visible light; on/offphoto cell; camera; general communication blocks such as (RS232;RF-RS-232; RS-422; RS-485;RF-RS-422; RF-RS-485); temperature sensor;pulse width modulator such as for modulated output based on thermostattemperature readings, PID control loops devices; buzzer; humidistat; andthe like. Up to two hundred and fifty six or more types of ACMs arecontemplated. Any four of the aforesaid ACM types allow a uniquecombination of I/Os (or circuitries) per IMB. If an additional four ACMsare required, then the ISB 14 can be connected to the IMB 12 and anotherfour ACMs 16B are added so as to increase the total number of ACMs toeight. Further repeating this, additional ISBs 14 can be added thusallowing the possible number of ACMs can be increased in multiples offour, thus twelve, sixteen and so on.

Each IMB12 and ISB14 includes four ACM connectors 18, although it ispossible that two ACM connectors can be used, each of which is typicallya 28 pin header. Other future connectors which can also be used include32 and 34 pin headers or more. The ACMs 16A/B are connectable to theirrespective IMB 12 or ISB 14 by a simple “plug-in” operation. The ISB 14is connectable to the IMB 12 using an I²C communications standard (notshown) via a base expansion connector 20, with the four ACMs 16B beingconnectable to the ISB 14.

As illustrated in FIG. 1A, the apparatus 10 can optionally be used witha smart plate cover 22 that can be temporarily plugged into the IMB 12.A smart plate cover interface 24 having a connector 19 for receiving theplate cover 22 allows the user to employ a user friendly programminginterpreter interface residing in the smart plate cover 22 to programthe apparatus 10. This allows for easy setup configurations to becarried out by the user via embedded generic functions enabling controlto the underlying ACMs 16A. Once the logic is created, the smart platecover 22 may be removed and stored until future programs are requiredwhile leaving the smart plate cover interface module 24 connected to itsIMB 12. The smart plate cover interface module 24 in essence is a modulethat extends the ACM connecter 18 and allows the connectivity of thesmart plate cover 22 via the connector 19.

FIG. 2 illustrates the apparatus 10 comprising the IMB 12 and four ACMs16A being used in a residential environment such as, for example, in aresidential single gang electrical box, where once the apparatus 10 isconfigured, the user can optionally remove the smart plate cover 22 andreplace it with a simple plate cover 21 designed as an open framesurrounding the ACMs 16A. The open frame allows the ACMs 16A to beviewed while leaving the smart plate cover interface module 24 exposed.This set up is advantageous when a user requires basic functionalitywhile retaining the ability for the ACMs to be interactive with the usersuch as, for example, an RS-232 port ACM or a button and status LEDsACMs and the like.

Now referring to FIG. 2A, an alternative apparatus design which may beuseful in homes includes an ACM16A which is fabricated as a one-pieceapparatus in which the smart plate 22 is integral with the ACM. Thisallows the user to purchase a single ACM with a smart plate cover as asingle one-piece component 23 which can then be plugged into the IMB 12via the ACM connector 18 thereby hiding the underlying modules. Thisalternative apparatus 10 is permanently used with the smart plate cover22 allowing the user to conveniently use the interface to control theunderlying ACMs.

It is to be understood that any smart plate cover 22 can be plugged intothe smart plate cover interface module 24. Referring now to FIGS. 3, 3B,3C, 3D and 3E any smart plate cover 22 can be plugged into the smartplate cover interface module 24 so as to hide the underlying ACMs. Thesmart plate 22 may be a basic model 26, which includes, for example, abasic color LCD touch screen indicator 27 and a plurality of dimmerswitches 29 for dimming lights in a room or other hardware devices.Moreover, when two IMBs 12 are required instead of one, a wider smartplate cover 22 would be used to hide the eight underlying ACMs. Theshape of the switches 29 or the sizes of the color TFT LCD screens maychange according to the aesthetic tastes of the user. A moresophisticated model 28 may include, for example, a larger touch screeninterface 31 which operates an integrated micro-computer for remotelycontrolling multiple systems throughout a house, such as for example,temperature control, lighting, door controls and the like. It iscontemplated that the apparatus 10, may be controlled via the smartplate 22 which can communicate via a control software operated fromcomputer readable medium. Thus, during typical use, the apparatus 10,when connected to the ACMs 16A/B, can be used for domestic controls aswell as controlling commercial/industrial systems such as machinery,heating, lighting and the like, regardless of whether a smart platecover is installed or not.

The programs, such as software kernels or Source code programs and data,which are within the IMBs and ISBs and the smart plates 22 may beupgraded using a personal computer or via a phone line over theinternet.

Still referring to FIG. 3, the basic model 26 and the sophisticatedmodel 28 may include additional detectors located around the smart plate22 frame of the models 26, 28 such as, for example, infra-red proximitydetectors 33, smoke detectors 35 and motion detectors and the like. Theproximity detectors 33 can be used to detect the location and movementof a hand relative to the detector 33. In some instances, movement ofthe hand within a pre-defined area relative to the detector may be usedto activate a specific system, such as lighting, whereas movement of thehand within another pre-defined area relative to the detector may beused to activate other systems or dimming actions.

Additional systems and hardware devices located remotely from the IMB12, which may be operated using the sophisticated model of smart plate26 or 28 (or models with color TFT LCD panels), include the followingnon-limiting examples:

-   -   Double pole switches; three way switches; four way switches;    -   Home utility timers for controlling lighting switches and plugs;    -   Motion detector (Each apparatus may detect motion and transfer        this information to all other apparatuses);    -   Heating thermostats with programmable set points;    -   LUX meter used to measure amount of visible light in a room so        to control light intensities;    -   Door buzzer activator (For single family dwelling to multi        family dwellings) condominiums and the like;    -   Photocell, internal/exterior temperature and humidity readings;    -   A vertical motion detector pointing up (for smoke detection) and        a vertical motion detector pointing down to detect foot, knee or        hand for controlling electrical loads;    -   Incorporation of a night light in every apparatus. The night        light will be made that the user can detach it and use it as a        flash light when power outages occur;    -   Telephone, Intercom and intrusion systems with camera;    -   Mirror (Image from integrated camera displayed on color LCD);    -   Random lighting activation when no-one home;    -   Smart tagging, smart card systems and car starter ;    -   Advanced security systems such as eye scanning/finger print        recognition;    -   Agenda/time/date/calculator/Long range weather        forecast/Internet/E-mail and utility screen savers when unit is        in wait mode or not in use;    -   battery charger;    -   Real time statistical analysis of main home electrical system        such as displaying hydro power consumption in watts, electrical        panel status, status of breakers in panel and amperage used per        breaker, phase out detection meaning, the system can warn the        user if a phase is disconnected, current status of main ground        meaning the system can warn the user if there is a faulty        service ground, resetting any panel breakers from any apparatus,        comparative power consumption reports from one year to another        and utility lists;    -   GPS capabilities; and    -   A series of programmable control function blocks such as AND        gate, OR gate, counters, set/reset variables, lag, mathematical,        PID and the like.

Still referring to FIG. 3, the infrared detectors 35 are orientated sothat one of the detectors points downwards towards the floor for humanhand/knee/foot detections and another pointing upwards towards theceiling for smoke detections. The detector pointing downwards 35 candistinguish if a hand is present (at a few inches below the smart plate)or if a knee is present (at two feet below the smart plate cover), or ifa foot is present (at four feet below the smart plate cover). The smartplate cover 22 can use infra-red detectors 33 to detect a frontal fingertap or hand-wave-to accomplish touch less switch control to control whatever loads are connected in the underlying modules and further controlsoftware actions within the IMB master CPU, IMB slave CPU or the ISBmaster CPU.

The infra red detectors 33 or 35 (so-called proximity or touchlesssensors or detectors) are integral with the smart plate covers 22 andcan be used to detect distance or the movement of a hand, knee or footrelative to the detector. In some instances, movement of the hand withina pre-defined area relative to the detector may be used to activate aspecific system, such as lighting, whereas movement of the hand withinanother pre-defined area relative to the detector may be used toactivate another system or dimming actions. At least two infra redproximity sensors (one facing the floor for foot, hand and/or kneedetections and one facing forwards for frontal hand, body or closeobject detections) are used as touchless sensors to control defaultsoftware sequences or default hardware actions such as on/off controlswhen the detection of a hand, knee or foot is waved once. Double ortriple or more hand, knee or foot wavings in a short period of time canfurther result in controlling different software or hardware actions.

The following outlines the logical result of the touchless wavingactions:

-   -   One wave signals an on/off control of a first electronic        hardware device such as default lighting, heating or motor loads        connected to the underlying ACMs;    -   One wave plus a paused detection is a signal to dim or reduce        the default lighting, lighting scene, heating or motor load        connected to the underlying ACMs;    -   Two consecutive waves allows the user to control a second        electronic hardware device such as a second lighting scene or to        control other loads such as heating, motors or other lighting        connected to the underlying ACMs of the apparatus 10 and/or        heating, motor or lighting loads connected to ACMs in other        apparatus 10 installed in remote electrical boxes or installed        in remote electrical equipment such as heaters and motor        housings;    -   Two consecutive waves plus a paused detection allows the user to        dim the second lighting scene or reduce/increase other loads        such as heating, motor speeds or other lighting connected to the        underlying ACMs of the current apparatus 10 or/and heating,        motor or lighting loads connected to ACMs in other apparatus 10        devices installed in remote electrical boxes or installed in        remote electrical equipment such as heaters and motor housings;    -   Three consecutive waves allows the user to control a third        electronic hardware device such as a third lighting scene or        control loads such as heating, motors or other lighting        connected to the underlying ACMs of the current apparatus 10        or/and heating, motor or lighting loads connected to ACMs in        other apparatus 10 devices installed in remote electrical boxes        or installed in remote electrical equipment such as heaters and        motor housings;    -   Three consecutive waves plus a paused detection allows the user        to dim the third lighting scene or reduce/increase other loads        such as heating, motor speeds or lighting connected to the        underlying ACMs of the current apparatus 10 or/and heating,        motor or lighting loads connected to ACMs in other apparatus 10        devices installed in remote electrical boxes or installed in        remote electrical equipment such as heaters and motor housings;    -   Additional consecutive waves allows the user to control        subsequent electronic hardware devices such as subsequent        lighting scenes or control subsequent loads such as heating,        motors or other lighting connected to the underlying ACMs of the        current apparatus 10 or/and heating, motor or lighting loads        connected to ACMs in other apparatus 10 devices installed in        remote electrical boxes or installed in remote electrical        equipment such as heaters and motor housings;    -   Additional consecutive waves plus a paused detection allows the        user to dim subsequent lighting scenes or reduce/increase other        loads such as heating, motor speeds or other lighting connected        to the underlying ACMs of the current apparatus 10 or/and        heating, motor or lighting loads connected to ACMs in other        apparatus 10 devices installed in remote electrical boxes or        installed in remote electrical equipment such as heaters and        motor housings.

Thus it is possible to control multiple electronic hardware devicesusing the touchless smart plate interface 22 having the proximitydetector 33, 35, in which the smart plate interface 22 is connected tothe modular apparatus 10 by: waving a hand at least once near theproximity detector to control operation of a first electronic hardwaredevice. Thereafter waving the hand at least once, pausing the hand nearthe proximity detector further controls operation of the firstelectronic hardware device. Two consecutive hand wavings near theproximity detector operates a second electronic hardware device and thentwo consecutive having wavings followed by a pause near the proximitydetector further controls operation of the second hardware device. Themethod may also include three consecutive hand wavings near theproximity detector operates a third electronic hardware device and threeconsecutive hand wavings followed by a pause near the proximity detectorfurther controls the third electronic hardware device.

One feature of the control method involves pulling the hand orthogonallyaway from the proximity detector so as to further control the electronicdevice. This is particularly useful if the user desires to dim thelights in a room or indeed fine tune the function of other electronicdevices described herein.

In another instance, the waving actions described above can be used toalso control internal logic sequences for specific tasks. Instead ofusing the pause to dim or reduce/increase loads as described above,another option is by varying the distance of a hand, knee or foot fromthe detectors located in smart plates 22. Furthermore, consecutive wavescombined with distance variations from the touchless detector willfurther control other hardware or software actions.

A long-range motion sensor for sensing movement and displaying amovement alarm on the screen, may further transmit these readings to theunderlying IMB/ISB/MUCX bases for further broadcasting this informationvia radiofrequency (RF) to other apparatus 10 devices installed inremote electrical boxes or installed in remote electrical equipment suchas heaters and motor housings. Included within the smart plate 22 arethe following:

-   -   thermostat for sensing heat and displaying the heat measurements        on the screen and may further transmit these readings to the        underlying IMB/ISB/MUCX bases for further broadcasting this        information via RF to other apparatus 10 devices installed in        remote electrical boxes or installed in remote electrical        equipment such as heaters and motor housings;    -   a lux meter (TAOS technology) for:        -   i) measuring visible light;        -   ii) measuring infrared light; or        -   iii) measuring visible or infrared light measurements on the            screen and may further transmit these readings to the            underlying IMB/ISB/MUCX bases for further broadcasting this            information via RF to other apparatus 10 devices installed            in remote electrical boxes or installed in remote electrical            equipment such as heaters and motor housings so to control            their operation based on the amount of visible light being            detected;    -   smoke detector (using infra red and/or photo electric and/or        ionization technologies) with on board alarm and displaying the        alarm(s) on the screen and may further transmit the alarm(s) to        the underlying IMB/ISB/MUCX bases for further broadcasting this        information via RF to other apparatus 10 devices installed in        remote electrical boxes or installed in remote electrical        equipment such as heaters and motor housings;    -   Doorbell buzzer system;    -   Video camera images of front door or any other rooms of a        dwelling or building may be broadcasted via rf to other        apparatus 10 devices installed in remote electrical boxes or        installed in remote electrical equipment housings;    -   humidistat for sensing humidity and displaying the humidity        readings on the screen and may further transmit these readings        to the underlying IMB/ISB/MUCX bases for further broadcasting        this information via rf to other apparatus 10 devices installed        in remote electrical boxes or installed in remote electrical        equipment such as heaters and motor housings;    -   camera so the apparatus can take pictures and store them in        memory or display them and may further be transmitted to the        underlying IMB/ISB/MUCX bases for further broadcasting this        information via RF to other apparatus 10 devices installed in        remote electrical boxes or installed in remote electrical        equipment such as heaters and motor housings;    -   intercom system used to record voice and may further transmit        the vocal sound message to the underlying IMB/ISB/MUCX bases for        further broadcasting this information via to other apparatus 10        devices installed in remote electrical boxes or installed in        remote electrical equipment such as heaters and motor housings;    -   intrusion system used to detect intruders by displaying intruder        alarms on the screen and may further transmit these alarms to        the underlying IMB/ISB/MUCX bases for further broadcasting this        information via RF to other apparatus 10 devices installed in        remote electrical boxes or installed in remote electrical        equipment such as heaters and motor housings;    -   camera allowing the user to take pictures and to display these        pictures on the screen and may further transmit the picture        images to the underlying IMB/ISB/MUCX bases for further        broadcasting this information via rf to other apparatus 10        devices installed in remote electrical boxes or installed in        remote electrical equipment such as heaters and motor housings;    -   A series of programmable control function blocks such as timer,        set, reset, lag, mathematical, PID and the like used for custom        programs via an on board TFT color screen's graphical user        interface programming language;    -   Permanent or/and detachable Nightlight;    -   Virtual switch creation can be accomplished by a pre-defined        graphical user friendly interface screen which can allow the        user to easily select any remote apparatuses 10 of his choice to        receive or transmit switching or dimming control via RF. For        example, a virtual switching and dimming control is a logic        sequence in the apparatus 10 that carries out the actions of a        single pole, double pole, three way, four way or five way (or        more way) switch or dimmer which can be used to control loads        such as heating, motors or lighting connected to the underlying        ACMs of the current apparatus 10 to any heating, motor or        lighting connected to remote ACMs of other apparatus 10 devices        installed in remote electrical boxes or installed in remote        electrical equipment such as heaters and motor housings;    -   Telephone and smart tagging systems; and    -   Displays readings associated to hot water tank(s) which        determine the amount of hot water available per tank.

All of the transmissions described above use a communications controlbus from the smart plates to the IMB/ISB/MUCX. The communicationscontrol bus, as will be described below, is used when bidirectionaltransmissions of 8 bit bus data are required, whereas a HUS is used forany analog or special signals.

Additionally, the apparatus 10 can incorporate emergency lighting foruse during hydro power outages. Also a detachable utility flash lightmay be associated with the smart plate cover 22. Also contemplated isthe use of a touch-button which can transform a portion of the smartplate cover 22 into a mirror using a miniature camera disposed in thesmart plate cover 22.

Additionally, the smart plate cover 22 may also include any combinationof the following features:

-   -   a graphical color touch screen (16/18/20/24 pixel color depth)        as shown in the smart plates 22. in which the graphical color        touch screen is used to display and operate the following        features:        -   display images which can be loaded from a desktop, laptop,            handheld computer or a USB memory drive to the IMB using an            RF link or a USB smart drive connection and thereby allowing            to further transfer data or images from the IMB to the smart            plate 22 via the MUC standard;        -   display dates, time, internal room and external            temperatures, long range forecasts, humidity levels;        -   display real time statistical analysis of the home            electrical system such as displaying hydro power consumption            in watts and electrical panel status. This information is            obtained by reading current and voltages from the home            electrical circuits connected within the electrical panel.            The current and voltage readings will be measured by a            remote apparatus 10 by the means of transducers connected            from the electrical circuits (using a current transformer            and electrical tappings) to the remote apparatus 10 and all            of which is installed within or close to an electrical            panel. This information may then be broadcast via RF to            other apparatuses 10 which will display the following            information:            -   status of breakers in panel and amperage used per                breaker;            -   phase out detection meaning, the system can warn the                user if a phase is disconnected;            -   current status of main ground meaning the system can                warn the user if there is a situation of faulty service                ground;            -   comparative power consumption reports from one year to                another and consumption utility lists which can compare                the power used for every apparatus 10;        -   to control all underlying ACMs;        -   an alarm clock or utility timer settings;        -   battery charger as an integral part of a smart plate;

Referring now to FIGS. 3E and 4, generally speaking, each room in ahouse has at least one domestic electrical box 32 located in a wall,typically near a doorway, which allow easy access and operation uponentry into the room. The box 32 is typically a single or multi ganged1104 electrical box which support plugs and switches for operatinglights, fans and the like. Other domestic boxes which can accommodatethe apparatus 10, include, but are not limited to, boxes such as a 4×4or a 4/11/16. The box 32 can house the apparatus 10 so that it isconnected via existing wires 34 to the electrical wiring network of thehouse (not shown). Advantageously, as best illustrated in FIG. 3E, theapparatus 10 located in the box 32 allows all of the electrical devicessuch as a clock, thermostat, intercom and the like to be moved into asingle location thereby allowing the user to control them from a singlelocation.

All IMBs can be hardwired to the electrical wiring network of the houseonly once by an electrician. Thereafter the choice of the underlyingmodules (ACMs) can be conveniently selected and plugged in by the userwithout electrical hazards or damage to the electrical system.Furthermore, the ACMs 16A/B can be replaced with different modules tosatisfy the user's specific needs. The IMB 12, the ISB 14 and the ACMs16A are sized and shaped to be located into the domestic electrical box32 (which can be single gang or multi gang configurations). Although theIMB 12, the ISB 14 and the ACMs 16A and 16B are generally illustrated ascuboid, it is to be understood that they may also be designed andmanufactured in other shapes and sizes as well, such as for example,slim cuboids so as to be located in space limited areas. For example, anACM 16A can be in the shape of a receptacle or a fixed decorative placemat or coaster because its underlying IMB/ISB bases are discretelyaccommodated. An ACM 16A may even extend itself taking the form of anextension cord. Thus, each electrical box 32 can accommodate an IMB 12with four ACMs 16A and one of the smart plates 26 or 28 can be pluggedinto one of the ACMs 16A so as to cover the electrical box 32. Thisprovides an aesthetically pleasing single control point from whichmultiple household devices can be remotely controlled, as bestillustrated in FIG. 3E.

Referring now to FIGS. 5, 6 and 7, a specific example of the modularapparatus 10 is provided in which a basic heat sink ACM module 36 isconnected to a dimmer ACM 40 and not to the IMB 12. The basic heat sinkmodule 36 includes three stacked heat sinks 38 located above the dimmerACM 40 and a smart plate cover interface module 24 into which the smartplate cover 22 can be plugged. The heat sink module 36 and the dimmerACM 40 may also be constructed as a one piece apparatus. The heat sinks38 are interconnected using wires 42 inside the heat sink module 36. Theheat sink module 36 is controlled by circuitry from the dimmer ACM 40.The dimmer heat sink load wiring 38A and 44 connect to the electricalwiring network as they overpass the IMB/ISB 12/14 as shown in FIGS. 6and 7. In the example shown, the minimum loading will be one load of 150watts at 120 VAC per heat sink. The example of this modular apparatuscan be located in the electrical box 32.

Referring now to FIG. 8, another example of the modular apparatus 10 isillustrated in which a slim slave base (SSB) module 46 is connected tothe IMB 12 via the base expansion connector 20. Three stacked heat sinks38 are connected to the dimmer modules 40 which contain the dimmingcircuits that control TRIACs integrated in the heat sinks 38. The SSB 46includes a plurality of access holes 48 for receiving the load wiring 44from each heat sink module 38. The load wiring 44 will go through theholes of the SSB 46 and connect to the electrical wiring in theelectrical box 32.

Alternatively, the SSB 46, as illustrated in FIG. 8A, includes screws 39which replace the load wires, and which are fixed on the heat sinkmodules 38 and can be screwed into the SSB 46. A TRIAC 49 is an internalelectronic component which is bolted onto the heat sinks. Each heat sinkmodule 38 comprises three heat sinks where each heat sink includes theTRIAC 49. The TRIAC 49 is responsible for controlling one electricalload. In the example illustrated, the TRIAC includes a pin out conductor51 which is connected to a screw instead of a long conductor, forexample a pin conductor from TRIAC 51 is welded to a washer 59. When theuser tightens the screw 39 by introducing a screw driver into a headscrew 63, the pin out conductor 51 is squeezed between washers 55 and 59by the exerted pressure produced from two cylinders 53 located aroundthe screw 39. Force will be produced at the top of the screw by the headscrew 63 and the bottom of the screw by a limit block 61 which is weldedto the cylinder 53 located at the opposite end of the head screw 63. Thelimit block 61 is compressed by the housing terminals 45 in the SSB 46and the head screw 63 allows for adequate screw 39 stability. Thismechanism will assure a good conductivity between the pin out conductor51 and the screw 39. Therefore, the user can safely and simply tightenthe screw 39 into the respective housing terminals 45 which extend fromone side of the SSB 46 to the other side allowing the user to join theelectrical wiring network 47 behind the SSB module 46. The screw housingterminals 45 accommodate the fixed screws 39 from the heat sink modules38 allowing connectivity and conductivity from the heat sink TRIACSlocated in the heat sink modules 38 to the electrical network behind theSSB 46. The electrical wiring 47 in box 32 is tightened under thehousing terminal head screw 45. The base expansion connector 20 isconnected to a special internal system bus of the slim salve base 46which is not related to the load wire connectivity hardware 44, 45 or47. When using the SSBs 46 as illustrated in FIGS. 8 and 8A, it isnoteworthy that the SSB does not contain any logical intelligence orelectronic circuits. The rational intent behind the SSBs' 46 hardwiretraces is to form the continuations of communication conductors (whichare power supply, CD88, HUS, and I²C) from, reading left to right, itsleft hand IMB 12 (or ISB) to its right hand ISB. Furthermore, the SSBextends the circuitry from one IMB to another while providing space forhardware such as heat sinks between IMBs and ISBs without loosing anycontrol or power signals from one base to another

It is to be noted that the same screw type mechanism described for FIG.8A may also apply to FIGS. 6 and 7 which demonstrates the apparatus in alow power configuration for a single gang 1104 box. This allows easyinterchangeability of the dimmer ACMs 38 without the user needing tomanipulate the electrical network wiring.

Referring to FIG. 8, in the example illustrated, the total load for theheat sinks 38 is a minimum of 150 watts per heat sink at 120 VAC. Inthis example, the IMB 12 includes two dimmer modules 40 (one of whichoffers control to 3 loads and one of which offers control to 6 loads),an RS232 ACM, and ACM 24 which is used to receive the smart plate covermodule 22. When used with the apparatus 10, the configuration in FIG. 8provides a high power configuration compared to the low powerconfiguration shown in FIGS. 6 and 7. The IMB 12 and the slave slim basemodule 46 are located in the electrical box 32, which in this case is a4×4 electrical box.

Referring now to FIG. 9, another example of the modular apparatus 10 isillustrated in which the heat sinks 38 are alternatively stacked andconnected to the smart plate cover 22 externally of the box 32. Anadditional plate cover 48 may be located over the heat sinks and mayinclude convection holes 50 locatable adjacent the heat sinks.

Intelligent Master Base (IMB) and Intelligent Slave Base (ISB)

Referring now to FIG. 10, the IMB 12 comprises a master centralprocessing unit called an IMB master CPU 52, which is connected to theIMB slave CPU 54 via I²C, a power supply 56 and an RF module 57, all ofwhich are mounted onto an IMB prototype circuit board (PCB) 58. The IMBmaster CPU 52 is used for global settings and controlling RF operationsand the IMB slave CPU 54 is used to communicate with the ACMs 16A. Afirst I/O bus 60 which is called the HUS (HUS will be later discussed indetails) interconnects the IMB slave CPU 54 to the four ACM connectors18. A first communication control bus 62, which I call a CD88communications standard (note that communications control bus and CD88communications standard are used interchangeably throughout thisdescription) also interconnects the four ACM connectors 18 to the IMBslave CPU 54. The CD88 will be described in more detail below. Typicalexamples of the IMB master CPU and the IMB slave CPU include, but arenot limited to, PIC, DSC/DSP micro-controller processors, 68 Series(Motorola), 8088 Series (Pentium), ARM processors and the like. In theexamples shown, the processors are PIC micro-controller or MCUs.

The ISB 14 comprises an ISB master CPU 64, a power supply 56, and fourACM connectors 68, which are also interconnected using a second I/O bus70 called the HUS and which is mounted onto a prototype circuit board(PCB) 72. The HUS will be described in more detail below. A secondcommunication control bus 71 also interconnects the four ACM connectors68. It is to be noted that the first and second communication controlbusses 62 and 71 are identical.

Thus, the ISB 14 comprises only one micro-controller called the ISBmaster CPU 64, whereas the IMB 12 comprises two micro-controllers CPUscalled IMB master CPU 52 and IMB slave CPU 54. It is to be noted thatthe IMB 12 and ISB 14 communicate via I²C through the base expansionconnector 20. The IMB PCB 58 and the ISB PCB 72 are mounted in theirrespective IMB and ISB 12,14 with their respective power supply 56 beingconnected to standard power wires at 120VAC (phase, neutral and ground)in the electrical box 32.

It is important to make the following distinction between the CPU's thatcommunicate by I²C and the CPU's that communicate by CD88 and HUS.Within the IMB 12, the IMB master CPU 52 and IMB slave CPU 54communicate via the conventional I²C industry standard. When any of theISB slave CPUs 64 communicate with an IMB master CPU 52, they also sharethe same two wire I²C bus. However, when a multiple universalcommunications extender (MUCX), as described below, is connected to anIMB or an ISB, the communications used will be via extended circuitriesof CD88 and HUS, thereby excluding the use of I²C.

The Communications Control Bus (CD88)

Referring now to FIG. 11, an embodiment of the communication control bus62 is illustrated disposed in the IMB 12. As described above, I havecalled my new communication control bus 62 a “CD88 communicationsstandard” in which the “CD” denotes Control/Data register and the “88”denotes “eight bits per control register and 8 bits per data register”.Each register in FIG. 11 is a serial in serial out with 8 bi-directionalI/O parallel bits 74HC299 device. The communication control bus 62comprises a network (or circuit) 74 having eight 8-bit shift registers76 which are electrically interconnected in a daisy chain manner using aplurality of I/O pins like 78 and wires 82. The eight 8-bit shiftregisters 76 include, in series, a first control register 84 and firstdata register 86; a second control register 88 and second data register90; a third control register 92 and third data register 94; and a fourthcontrol register 96 and fourth data register 98. The shift registers 76are arranged in pairs, thus the first control register 84 and the firstdata registers 86 are one pair, the second control register 88 and thesecond data register 90 are another pair and so on. Each controlregister and data register pair are connected to its corresponding ACMconnector 18, such as for example, the second control register 88 andthe second data register 90 pair, are connected to an ACM connector, asbest illustrated in FIG. 11. Each register is a serial in serial outwith 8 bi-directional I/O parallel bits 74HC299 device.

The IMB slave CPU 54 in the IMB 12 comprises six IMB slave CPU I/O pins100 for serially communicating 13 bits of data to each of the four ACMconnectors 18 (also known as MUC ports), as will be explained in moredetail below.

Six wires (listed below) lead from the six IMB slave CPU I/O pins 100which connect the IMB slave CPU 54 to the eight 8-bit shift registers76. The six wires include:

-   -   Wire #1: Clock#1 102    -   Wire #2: Enable 104    -   Wire #3: Clock#2 106    -   Wire #4: SL1 108    -   Wire #5: SL2 110    -   Wire #6: DQA Feedback 112

The clock #1 wire 102 and the enable wire #2 104 connect the IMB slaveCPU 54 to the first, second, third and fourth control registers 84, 88,92 and 96 and transmits clocking and enable data signals to each controlregister. The SL1 wire #4 108 and the SL2 wire #5 110 respectively areoutputs from the IMB slave CPU 54 which transmit serial data signals.The SL1 wire 108 signal is connected to a serial input pin 114 (the SL1input pin) of the first control register 84. The SL1 input pin 114 canserially take in 8 bits at one time without loosing the states of thebits. Similarly, the SL2 wire #5 110 is connected to an SL2 input pin116 in the first data register 86. The SL2 input pin 116 can alsoserially take in 8 bits at one time without loosing the states of thebits. The clock #2 wire 106 connects the four data registers 86, 90, 94and 98 to the IMB slave CPU 54 and transmits clocking data signals therefrom to each of the data registers. The DQA feedback wire #6 at 112which is connected to the DQA-output pin 118 of the fourth data register98 is connected to the IMB slave CPU 54 and feeds serial data backthereto.

Thus, the communication control bus 62 comprises the aforesaid six wires102, 104, 106, 108, 110 and 112, which communicate data signals from theIMB slave CPU 54 to the eight 8-bit shift registers 76 in the network(or circuit) 74. Two eight bit shift registers, namely each pair of thecontrol and data registers, such as for example the first controlregister 84 and the first data register 86, are associated with each ACM16A thereby providing each IMB 12 with the ability to connect to up tofour ACMs 16A/B.

The 13 Bit Bus

Referring to FIGS. 11, 13 and 14, each pair of control and dataregisters comprises a 3 bit command bus 122. For the sake of clarity,since each 3 bit command bus is identical, only one will be described indetail with reference to the third control register 92 and the thirddata register 94, as illustrated in FIG. 13. The 3 bit command bus 122is a 3 wire link between the control register 92 and the data register94 which issues command signals for the data register 94. Since theeight 8-bit shift registers 76 are arranged in pairs, in which thecontrol register controls its adjacent data register, as illustrated,the 3 bit command bus arrangement is repeated for each pair. Threeconnector wires 128, 130, and 132 interconnect the control register 92with the data register 94 via three control connector pins per register.The control pins 134, 136, and 138 are located on the control register92 (which are the 3 most significant bits of the control register) 126and the control pins 140, 142, and 144 are located on the data register94 (which are input control signals for the data register device). Thecontrol register 92 uses its five least significant bits 124 asadditional outputs that can be used as complementary signals. The dataregister 94 uses its 8 bit bi-directional I/O parallel bus 125 tocommunicate 8 bits at a time. Therefore, 8+5=13 bits, 8 of them formingthe 8 bit bi-directional I/O bus from the data register 94 and 5 ascomplementary outputs from the control register 92 equates to one 13 bitbus per ACM connector 18. (124+125). The five bits 124 of the controlregister 92 are outputs only, which can be used as optional controlsignals on the PCB 58 or PCB 72 at 18 or 68 which connect to the ACMs16A/B. The eight bits 125 of the data register 94 is a bi-directional 8bit bus, which is used on the PCB 58 or PCB 72 which connect to the ACMs16A/B at 18 or 68. Therefore, each register pair (control/dataregisters) produces a 13 bit bus.

The ACM Connector

As illustrated in FIG. 13, each 13 bit bus 124, 125 originating fromeach paired registers (control/data) communicates with one of the fourACM connectors 18/68 which are integrated in each of the IMBs 12 andISBs 14.

Referring now to FIGS. 10, 11 and 17, each ACM connector 18/68 are 28pin headers. The IMB slave CPU 52 also offers resources called HUS 66,shown as first and second I/O buses 60 and 70 in FIG. 10. It is to benoted that the house icons in FIG. 11 illustrate that the signals at theHUS 66 originate from signal connections located at 56 which connect tothe IMB slave CPU 54. Furthermore, for the sake of clarity, it is notedthat HUS is not part of CD88. The HUS is a separate set of resourcesthat can be used in parallel with CD88 which may be required by an ACM16A/B and comprises the following:

-   -   2—RS-232 ports;    -   4—Analog/Discrete inputs;    -   1—I²C communications (not related to the I²C in the base        expansion connector);    -   1—Pulse width modulation; and    -   1-6—I/Os used for reserved special system logic signals

Referring now to FIG. 17, the CD88 standard includes pins #14 to 26,whereas the hardware utility signals (HUS) includes pins #3 to #9 , #11to #13 and pins #27-28. Pins #1, #2 and #10 are dedicated powerconnections. Thus each ACM connector 18 or 68 provides the followingservices:

Pin#1: Ground (Power connections)

Pin#2: +5 VDC (Power connections)

Pin#3: Analog input (HUS)

Pin#4/5: RS232 (TX/RX) (HUS)

Pin#6/7: Special discrete inputs used to detect RS-232 ACM's (HUS)

Pin#8/9: I2C (SCL/SDA) (HUS)

Pin#10: Battery back up power (Power connections)

Pin#11: Module variation flag (For future to detect possible ACMvariations) (HUS)

Pin#12/13: Reserved system utility inputs (HUS)

Pin#14-18: CD88, five (5) user control output bits from controlregisters

Pin#19-26 CD88, eight (8) bit data byte from data registers

Pin#27: Pulse width modulation output (HUS)

Pin#28: CD88_Read_Flag (HUS)

How the ACMs are Identified

The IMB 12 or ISB 14 can identify which ACM 16A is plugged in. Each ACM16A has a hardwired coded address which appears in the data register'sbus. Each bit of the bus is either a logical “1” or a logical “0” byusing either a parallel pull up or pull down resistor respectively, asdescribed below. When manufactured, a predetermined numericalcombination of the eight bit states becomes the ACM's permanent address.Furthermore, some of the ACMs have an eight bit bus control buffer whichis controlled by the first bit of the control register. An ACM that onlyneeds the use of the hardware utility signals (HUS), will use the CD88communications standard to only dispatch its address. However, if theACM uses the CD88 communications standard to convey data as well, thenan eight bit bus control buffer is incorporated in its design. In thecase where the data register's bus is to be used to exchange datainstead of the module's address, the eight bit bus control bufferlatches in the data byte overriding the eight bit address. Therefore, inthis case, the data register bus is used to transfer data only. Thisoverrides the address bits because the 8 bit lines are connected toeight separate pull up/down resistors. Similarly, if only the address ofthe ACM is required, then the eight bit bus control buffer unlatches thedata information byte leaving only the reflection of the ACM's eight bitaddress on the data register's bus. Thus, the data register bus is usedto obtain the ACM's address at one instance and convey data at anotherinstance.

As best illustrated in FIG. 16, an ACM circuit 156 is located in eachACM 16A which compliments the CD88 communication standard and HUSservices. The circuit 156 comprises an eight bit data bus portion 158 ofthe 13 bit bus. The eight bit data bus 158 originating from the IMB 12,includes wires 160 which splits in two different routes, the first being166, and the second being to an 8 bit bus. The first route 166communicates with eight parallel pull up or pull down resistors 168,depicting the permanent address of the ACM 16A. The second route 164communicates with the control buffer 162. A buffer latch control 167connects the control buffer 162 with the first bit of the controlregister.

Therefore, each bit of the eight bit data bus 158 will tap to the pullup/down resistor 168, which forms the address of the ACM 16A/B. If theACM 16A also requires 8 bit data communications, each bit will also tapinto an eight bit control buffer 162. The eight bit bus control buffer162 is not part of the CD88 communication standard. The CD88communication standard goes from the IMB slave CPU 54 to the four ACMaddresses (which are the resistors). Thus, the eight bit bus controlbuffer 162 is only installed in the ACMs 16A when it is required to usethe eight bit data bus 158 to retrieve the address of the ACM 16A in oneinstance and to use the eight bit data bus 158 as a generalbi-directional parallel eight bit data transfer bus in another instance.

Thus in sum, the CD88 communication standard allows the exchange ofinformation from the six wires 102, 104, 106, 108, 110 and 112 from theIMB slave CPU 54 or ISB master CPU 64 to 13 bits of information to anyof the four 13 bit buses which connect to any ACM connectors 18simultaneously or one at a time. Without the CD88 communicationsstandard, the IMB slave CPU 54 or ISB master CPU 64 would need up to 52discrete hardware I/O resources. It is contemplated that the CD88communication standard can be modified to use one 16 bit controlregister and one 16 bit data register thus improving the efficiency ofthe CPU I/O resources. In the case where 16 bit control and dataregisters would be used, the communication standard would be namedCD1616 and would be able to obtain 116 I/Os from the six wires 102, 104,106, 108, 110 and 112 from the IMB slave CPU 54 or ISB master CPU,where:

Control register: (16 − 3 command bits) = 13 bits Data register: = 16bits 29 bits Multiplied by 4 ACM connectors: × 4 ports 116 I/Os total

Without using the CD88 communications standard, to obtain 116 I/Os in abus like structure from a standard 8 or 16 bit CPU, would requireconsiderable bus circuitry component customization. To integrate 116I/Os in a CPLD would be prohibitively expensive. The CD88 communicationsstandard allows a large number of I/Os structured as multiple 13 bitports to communicate between the IMB slave CPU 54 (or ISB master CPU 64)and a plurality of different types of electronics circuitssimultaneously or one at a time. In order to achieve the ultimate spaceefficiency, the production design for the registers implicated for theCD88 communications standard, will be integrated in a CPLD.

Multiple Universal Communications (MUC) and Multiple UniversalCommunications Expanders (MUCX)

Referring now to FIGS. 19 and 20, a communications control bus CD88 201,a HUS 204, and power connections (not shown) of an ACM connector 18 aredefined as 1 MUC 202. FIG. 20 illustrates four MUCs 203 per IMB 12 (orISB 14).

A MUC (Multiple universal communications) defines the communicationscomponents wired into the ACM connector. The CD88, HUS and powerconnections make up the MUC, thereby creating a MUC standard. Asillustrated in FIG. 20, each IMB incorporates four ACM connectors, whichallows the MUC standard to be repeated four times per IMB/ISB.

Referring to FIGS. 18 to 23, in which an alternative embodiment of theapparatus of the present invention is illustrated at 200. The apparatus200 can be further expanded using a multiple universal communicationsextender (MUCX) 202. The MUCX 202 expands the CD88 circuit via the baseexpansion connector 20 which allows the CD88 circuitry to be doubledthereby obtaining a total of eight MUCs (8 control registers and 8 dataregisters). The base expansion connector 20 may also be used to conveypower connections 211, I²C 213, HUS 215 and CD88 circuitry 217 as shownin FIG. 23. Every MUCX added, will increase the ACM connectors by four.The reason one would use a MUCX compared to using an ISB is to offer alower cost solution for less efficiency. Also the HUS's resources areshared between the adjacent base (reading left to right) and everysubsequent MUCX that is appended. MUCX's only include a CPLD whichincorporates the extended CD88 circuitry, thus making it less expensivebut slower.

When a MUCX is used, the IMB slave CPU (or the ISB master CPU) mustissue enough serial data bits to program sixteen registers instead ofeight. For example, as shown in FIGS. 21 and 22, from the IMB slave CPU54 located in the IMB 12, two supplementary 16 bit data streams arerequired to send signals to an additional available circuit 206comprising an additional eight 8 bit shift registers 208 included in theMUCX. The additional shift registers comprise, in pairs, a fifth controlregister 210 and a fifth data register 212; a sixth control register 214and a sixth data register 216; a seventh control register 218 and aseventh data register 220; and an eighth control register 222 and aneighth data register 224. Each of the aforesaid pairs of registerscomprise the 13 bit bus, (CD88) which together with the hardware utilitysignals 228 (HUS) and the power supply connections 226, provide theoutlets in the MUC via the ACM connector.

Referring to FIGS. 24 and 24A, two ACMs are connected to theirrespective ACM connectors 18. The ACM 250 is an RS232 module which onlyrequires the 8 bit address to be reflected on the data register's bus160 so it can be identified. It also requires the RS232 peripheral(included in the IMB slave CPU's resources) portion of the HUS therebycommunicating the RX/TX RS232 signals to the RS232 driver allowing theuser to connect himself using a standard DB9 connector. Another ACM 252may be an 8 bit digital signal to 2 seven segment displays whichrequires no HUS, but requires the data register's 8 bit bus to conveyits address in one instance and in another instance convey data to besent to the specific ACM's circuit which converts it to a 2 digit valueon the two seven segment displays. The control register contributes tothe ACM's circuit 254 as a control output which is used to control logiccircuitry in the specific ACM's circuit 256.

Detailed Operation of CD88

A loading and unloading operation using a serial manipulation in thecommunications control bus 62, 71 will now be described in detail withreference to FIGS. 11 through 14. The control and data registers canoperate in two modes, namely the shift left and shift right modes. Forease of description, only the shift right mode will be described. Theeight 8-bit shift registers 76 are arranged in pairs in which thecontrol register controls its adjacent data register. Once the controlregister is serially loaded, its 3 most significant bits will beoutputted to the three wires 128, 130, and 132 which interconnect thecontrol register via the three control pins per register, namely pins134, 136, 138, 140, 142, and 144. This provides a three bit data commandfrom the control register to its adjacent data register.

Before the data registers 86, 90, 94 and 98 can be loaded or unloadedwith data, each control register 84, 88, 92 and 96 first transmits a 3bit disable command signal to its adjacent data register via 122 toprepare it for incoming data. This instructs the data register toprepare itself to allow data to be serially loaded in or unloaded out.To achieve this, the three control pins interconnect each controlregister to its associated data register, as best illustrated in FIGS.11, 13 and 14. Disabling the data register causes the data register'sinternal logic to enable its serial clocking mechanism. Thus, to loadall four data registers, the control registers must instruct all thedata registers to be disabled before the data registers can be loaded.

In sum, referring to FIG. 13, before the data registers 86, 90, 94 and98 can be loaded with data, the control registers 84, 88, 92 and 96 arefirst serially loaded with their data bytes in which the three mostsignificant bits of these bytes will be the command signal for therespective data register. The three most significant bits of the controlregister are a specific command that instructs the data register whataction it should carry out. Following receipt of the disable command,the data registers 86, 90, 94 and 98 can then be loaded serially.

Referring to FIGS. 11 and 12, (for clarity purposes, the 3 bit commandsignal has been omitted from FIG. 12) during loading of the controlregisters 84, 88, 92 and 96, a first 32 bit stream of data (1011 00011010 0000 1110 1101 0000 1010) 146 is serially transferred from the IMBslave CPU 54 to the control registers 84, 88, 92 and 96 via the SL1 wire108 in the direction of arrow A. Every clock from the clock #1 wire 102shifts a bit of data from the IMB slave CPU to the control register'sSL1 input pin 114. Thus, using the first in first out (FIFO) order, (theright most byte being the first data byte at 146), the first 8 bit databyte will be received in the first control register as 0101 0000, thesecond 8 bit data byte will be received in the second control registeras 1011 0111, the third 8 bit data byte will be received in the thirdcontrol register as 0000 0101 and the fourth 8 bit data byte will bereceived in the fourth control register as 1000 1101.

The data registers are now ready to be loaded as follows. During loadingof the data registers 86, 90, 94 and 98, a second 32 bit stream of data148 (0000 1111 1110 1010 1111 1110 0000 0011) is serially transferredfrom the IMB slave CPU 54 to the data registers via the SL2 wire 110.Every clock from the clock #2 wire 106 shifts a bit of data from the IMBslave CPU to the data register's SL2 input pin in the direction shown byarrow B in FIG. 12. Thus, using the first in first out (FIFO) order,(the right most byte being the first data byte 148), the first 8 bitdata byte will be received in the first data register as 1100 0000, thesecond 8 bit data byte will be received in the second data register as0111 1111, the third 8 bit data byte will be received in the third dataregister as 0101 0111 and the fourth 8 bit data byte will be received inthe fourth data register as 1111 0000.

The SL1 input pin 114 can serially receive 8 bits at one time withoutloosing the states of the bits. If, for example, a ninth bit is clockedinto this serial input of the first control register 84, then the firstbit is sent to the input of the next control register via CQ1 output ofthe first control register. Similarly, the SL2 signal 110 is connectedto the SL2 input pin 116 of the first data register. This pin can alsoserially receive 8 bits at one time without loosing the states of thebits. If for example, a ninth bit is clocked in to this serial input ofthe first data register 86, then the first bit will be sent to the inputof the next data register via the DQ1 output of first data register.Using the clock signal clock#1 102, 32 clocks will be required for the32 data bits at 146 to serially travel via the SL1 wire 108 to theserial input of the first control register 84 and continue through thesubsequent control registers 2, 3 and 4 thereby filling their contentswith data from 146. Similarly, using the clock signal clock#2 106 willalso require 32 clocks for the 32 data bits at 148 to serially travelvia the SL2 wire 110 to the serial input of the first data register 86and continue through the subsequent data registers 2, 3 and 4 therebyfilling their contents with data from 148.

Thus in sum, loading the control registers requires that the SL1 wireissues a first stream of 32 serial bits 146 in a single operation. Thecontrol registers where the serial output pin 78 (CQ1) of the firstcontrol register 84 is daisy chained to the input pin of the secondcontrol register 88. Furthermore, the serial output pin of the secondcontrol register 88 is daisy chained to the input pin of the thirdcontrol register 92. Finally, the serial output pin of the third controlregister 92 is daisy chained to the input pin of the fourth controlregister 96. Also, loading the four data registers 86, 90, 94 and 98,the SL2 wire must also issue a second stream of 32 serial bits 148 in asingle operation and the aforesaid process is repeated for the dataregisters.

To unload the data registers 86, 90, 94 and 98, another 3 bit disablecommand code signal is transmitted by the control registers to the dataregisters. Thereafter, the DQA wire #6 112, which is connected to theoutput of the fourth data register 98 feeds a stream of 32 bits backinto the IMB slave CPU 54, thereby allowing the IMB CPU 54 tosystematically store this data in a table defined by its internal logic.However, only the data registers can unload their bytes to the IMB slaveCPU 54. Conversely, the control registers cannot unload their bytes tothe IMB slave CPU since there is no feedback wire.

Loading and Writing to Buses

As described above, the CD88 communication standard requires that thecontrol registers 84, 88, 92 and 96 are first loaded before the dataregisters are loaded because once the control registers are loaded, the3 most significant bits of their contents act as the commands destinedfor the adjacent data registers.

Referring now to FIGS. 13, 14, and 15, the following is a list of thefour possible control register commands from the three most significantbits 126 to the data register 94 via the three wires 128, 130 and 132,which instructs what action each data register will take:

CONTROL REG COMMANDS (3 MSB) DATA REGISTER MODE 1) 1000 0000 Write 2)0000 0000 Clear 3) 1100 0000 Read 4) 1010 0000 Disable

The “write” mode causes the data register to parallel output its 8 bitbyte. The “clear” mode causes the data register to clear its parallel 8bit byte (sets all bits to “0”). The “read” mode, instructs the dataregister to do a parallel read of the 8 bit byte. The “disable” modesets the data register to high impedance, as illustrated in FIG. 15.

Referring to FIG. 14, alternatively it is possible to disable the dataregisters and unload their contents to the IMB slave CPU 54. In thisoperation, it is assumed that the internal contents of all the dataregisters are FFH (1111 1111). Firstly, the control registers are loadedwith their data bytes 85 whereby the three most significant bits of eachcontrol register will be a first disable command for its adjacent dataregister (1010 0000). Secondly, the data registers are then seriallyunloaded through the DQA wire #6 112 causing the 32 bit stream of “1”s87 to be received by the IMB slave CPU 54.

In sum, once the data registers are loaded, from the IMB slave CPU theycan be instructed to output their contents to the outside world via theACM connectors 18. The opposite is also possible where, once the dataregisters are loaded with data originating from the outside world viathe ACM connectors 18, they can be instructed to serially transfer theircontents to the IMB slave CPU via the DQA feedback wire.

Referring to FIG. 15, an example of the operations described aboveinvolves loading all the data registers with different values from theIMB slave CPU and then outputting the values stored in the second andfourth data registers 90 and 98 to their respective 8 bit bus whilesetting the first and third data registers to high impedance. The seconddata register 90 will output the value of HEX CC (1100 1100) and thefourth data register 98 will output the value of HEX 33 (0011 0011). Thefirst and third data registers 86 and 94 will be set to all “0”s. So tobegin, in this example the control registers 84, 88, 92 and 96 are firstloaded with their data bytes whereby the three most significant bits ofthese bytes will be the command for the adjacent data register. All thecontrol registers are first loaded with a 32 bit stream containing thedisable command for all the data registers. Thus, in this case a first32 bit 150 serial operation is:

1010 0000 1010 0000 1010 0000 1010 0000 disable disable disable disable

As described above, when the disable command above is sensed by the dataregister, the data register's internal logic enables its serial clockingmechanism.

Following the disabling of the data registers, a second 32 bit 152serial loading operation of all the data registers is done with thecorresponding output values. Thus the second 32 bit 152 serial operationis:

0000 0000 1100 1100 0000 0000 00110011 Data (0) Data (HEX CC) Data (0)Data (HEX 33)

To output the values from the second and fourth data registers 90 and 98to their respective 8 bit bus, another 32 bit stream 154 is issued whichwill make the first and third control registers 84 and 92 contain adisable command, while on the other hand making the second and fourthcontrol registers 88 and 96 contain the write command. Thus the third 32bit 154 serial operation is:

1010 0000 1000 0000 1010 0000 1000 0000 disable Write disable Write

Immediately after the control registers are filled with the third 32 bit154 stream, the two “disable” and the two “write” commands will beissued to their respective data registers which in turn will disable thefirst and third data registers 86 and 94 and output the HEX values of CCand 33 HEX on the data register buses connected to the second and fourthdata registers 90 and 98. Each pair of control and data registerscorrespond to their respective ACMs 16A or 16B thus affirming that onecontrol register and one data register per ACM 16A or 16B is required.In this example we did not take advantage of the 5 least significantbits of the control registers.

In another example of an operation, the data registers 86, 90, 94 and 98are set to read in the contents of their respective external buses intothe data registers and then unload the data registers to the IMB CPU 54.Firstly, all the control registers 84, 88, 92 and 96 are loaded with a32 bit stream to set the all the data registers in read mode. In thiscase the data registers need not be disabled since they don't requiretheir serial mechanism to be enabled). Thus the first 32 bit serialoperation is:

1100 0000 1100 0000 1100 0000 1100 0000 read read read read

Thereafter, all the control registers are again loaded with another 32bit stream to disable all the data registers since the enabling of thedata register's serial mechanism is required next. Thus the second 32bit serial operation is:

1010 0000 1010 0000 1010 0000 1010 0000 disable disable disable disable

Then a 32 bit unload command is issued to all the data registers to loadthe contents loaded form their respective 8 bit buses. Thus the 32 bitserial operation is:

1010 1010 1010 1111 1111 0000 1111 1111 data data data data

Immediately after the data registers are unloaded to the IMB CPU 54, theIMB CPU 54 will systematically store the bytes in configuration tablesthat are created to service logic corresponding to the data read fromthe ACMs.

Referring now to FIGS. 21 and 22, the loading and unloading operation ofthe registers in the alternative embodiment of the apparatus 206 isessentially identical to that described above, the only difference beingthat eight additional registers and 64 bit data streams are used due tothe addition of a MUCX.

Referring to FIG. 32, the wires #1,2,3,4,5,6 and items 84, 86, 800 and801 in the circuit are embedded in a MAX II CPLD and repeated 4 times soto achieve the complete CD88 communication standard circuit. This allowsthe CD88 communications standard to fit in minimal space. Externalcomponents 18 and 802 are not embeded in the CPLD: The A_QA_D1, B_QB_D1,C_QC_D1, D_QD_D1, E_QE_D1, F_QF_D1, G_QG_D1 and H_QH_D1 bidirectionalpins is the typical data register's bus for every CD88 register pairs.However, before these outputs connect to the ACM connector 18, they alsoeach connect to a 47 Komh pull up resistor. This allows the IMB SlaveCPU to read in all high's (FFh) value when no ACM is plugged in. Thefive outputs (A/QA, B/QB, C/QC, D/QD and E_QE) of the control registershave three possible states which are HIGH (1), LOW (0) or high impedance(HZ). In the event where the control register is disabled by setting theWire #2, 104, to a HIGH value, the 74299 sets its outputs to a highimpedance state, which may cause logic circuits connected to the A/QA,B/QB, C/QC, D/QD and E_QE to act in an unpredictable manner. Therefore,to avoid this, a VHDL logic block is inserted between the five outputs(A/QA, B/QB, C/QC, D/QD and E_QE) of the control register 84 and theterminals on the ACM connector A_QA_C1, B_QB_C1, C_QC_C1, D_QD_C1,E_QE_C1. The VHDL block carries forwards the logic in the followingtruth table:

Illustrated below is a truth table for one output pin from a controlregister :

WIRE #2 104 A QA A QA C1 1 HZ 1 0 1 1 0 0 0

This is identical for B_QB to E_QE outputs of all the control registers.

Furthermore, when the control register is disabled as discussed above(Wire #2, 104 is HIGH), the 74299 also sets the F/QF, G/QG and H/QH to ahigh impedance state. Therefore in this situation the data register'sinputs 86 (CLRN, S0 and G1N) would see high impedance (HZ). This problemwas overcome by building a logic circuit comprising three OR gates andtwo exclusive OR gates 801 to obtain the correct 3 bit reflection 126from the control register 84 to the data register 86.

Therefore when the control register is disabled, the data register readsa 3 bit write command thus a high for its reset (CLRN) input 128, a lowfor its read (SO) input 130 and a low for its DISABLE (G1N) input 132.Hence in this case, the data register would be set to its default stateof write mode which is what the CD88 requires while the control registeris being disabled.

A logic gate particularity must be pointed out where when an OR gateor's a HZ state and a HIGH value, the result will always be HIGH.Therefore, when the control register 84 is disabled via Wire #2 ,104,the 74299 immediately sets all its outputs A/QA to E/QE and the F/QF,G/QG and H/QH outputs to a high impedence state HZ. At this point, OR1sees HZ at F/QF and when read with a TRUE value from wire #2, 104, theresult will validate to a TRUE at the output of OR1 which is furtherexclusive ored (XOR1) with wire #2 ,104 resulting in a FALSE value atthe output of XOR1 which is applied to the G1N input of the dataregister 86. The same logic applies to OR2 which results to a FALSEvalue at the output of XOR2 which will be applied at the SO input of thedata register 86. Also, OR3 sees HZ from H/QH and when ored with a TRUEfrom wire #2, 104, the result will validate to a TRUE at the output ofOR3 resulting in a TRUE value being applied at the CLRN input of thedata register 86.

Also, the logic gates at 801 of FIG. 32 can maintain the clear, read anddisable 3 bit data register mode commands while the control register isenabled. The required command bits are illustrated below during enabledand disabled instances of the control register.

(3 MSB) DATA CONTROL REGISTER CLRN SO G1N register mode DISABLED (Wire#2= high) 1 0 0 Write “default reset state” ENABLED (Wire#2 = low) 1 0 0Write ENABLED (Wire#2 = low) 0 0 0 Clear ENABLED (Wire#2 = low) 1 1 0Read ENABLED (Wire#2 = low) 1 0 1 Disable

Note that the SO (Read bit) input of the data register is also reflectedto pin 28 of the ACM connector called “CD88_Read_Flag” which is used tosignal any ACMs that the register pair is in read mode.

Serial Pillar to Nodes Transmission (SPNT)

Referring to FIGS. 28 and 29, a serial pillar to nodes transmission(SPNT) is a nodal network protocol for transmitting and receiving datain a uniline format between two or more nodes via RF communications asshown at 500 of FIG. 28. Each node is an IMB which comprises an RFtransceiver chip such as the EMBER EM260 connected to the IMB Master CPUas illustrated in FIG. 10. The EM260 from Ember is a ZigBee NetworkCo-Processor that combines a 2.4 GHz IEEE 802.15.4 compliant radiotransceiver with a flash-based microprocessor running the EmberZNetZigBee stack. With a fast SPI-based interface to an applicationmicroprocessor, the EM260 allows easy addition of ZigBee networking tothe apparatus 10.

SPNT is made up of two or more nodes where one of the nodes must beconfigured as a Pillar transmission module(PTM) 501. This is the modulethat will be responsible for initially detecting all other existingnodes involved in its communication environment which is a nodal networkenvironment (NNE). The detection procedure is denoted as the nodalnetwork registration procedure (NNRP). After finishing the NNRP, the PTMis responsible for commencing the transmission of one long serial streamof bits which contains information for all the nodes. FIG. 29 shows theSPNT network in its initial state 507. For example, each node mayrequire 50 bits of information and if 4 nodes have been detected duringby the NNRP, the pillar node 501 will transmit a serial stream of 200bits long in one operation via an RF transmission in the direction shownby the arrows 506A.

Therefore, at 508, upon completion of the 1^(st) SPNT operation, node505 will contain bits ranging from bit #151 to 200, node 504 willcontain bits ranging from #101 to 150, node 503 will contain bitsranging from bit #51 to 100 and node 502 will contain bits ranging frombit #1 to 50. In summary, the 1^(st) 50 bits of serial data transmittedby the PTM must pass sequentially from node to node until the 50 bitsreach their destination at node 505. Similarily the 2^(nd) set of serial50 bits must pass sequentially from node to node until the 50 bits reachtheir destination at node 504. This process continues until all thenodes recieved their respective 50 bits. Once the 200 bit stream hasbeen completely broadcasted by the PMT 501, the PMT's transmissionbuffer 510 will be empty and contain non relevant data depicted as “x”.

Upon the completion of the 1^(st) SPNT operation described above, allthe nodes will read and modify their respective 50 bits of dataaccording to their specific requirements and prepare to dispatch anupdated set of 50 bits for the 2^(nd) SPNT transmission. At this time,every node is instructed to update special “return ready flags” whichwill be used to confirm the validation of the 50 bits.

The 2^(nd) SPNT transmission actually loads the 200 bit stream which iscomprised of nodes 502, 503, 504 and 505 back into the PTM 501 via an RFtransmission in the direction of depicted by 506B in the same serialsequence described above. After the 2^(nd) SPNT transmission iscompleted the state of the node's data can be viewed at 509 of FIG. 29.At this point, software analyses of the bits loaded in the PTM 501 arecarried out by the PTM where the data bits are interpreted andmanipulated by respective logic routines. Thereafter, the regenerationof a new 200 bit stream is executed and the aforesaid process repeatsitself for further communications with its nodal network environmentonce again.

Also, at any time, after an SPNT transmission in the direction of 505Ais carried out, any node can enter a continuous private broadcastingoperation with one, several or all other nodes within the nodal networkenvironment.

In the case where a sixth node is introduced in the nodal networkenvironment, the serial stream will be adjusted to 250 bits. Anunlimited amount of nodes can be appended or removed from the networknodal environment.

In the event that a node becomes disfunctional due to software problemsor physical damage, the previous node will automatically establish RFcommunications with next node bypassing the faulty node therebycontinuing the serial stream operations.

In the event where the PTM node becomes disfunctional due to softwareproblems or physical damage, the next node in line will be ordered totake over the PTM's sequence of operations and will become the new PTMfor the nodal network environment.

SPNT bit definitions may be but not limited to:

BITS DESCRIPTION BIT SIGNIFICANCE 1 to 10: Node ID 11 to 12: Statusregister BIT#7: Return Ready flag BIT#6: Node private communication flagBIT#5: Valid data flag (Whether PTM should use data or not) BIT#4:Repeat flag (Error orccured, please repeat!) BIT#3: CD88 busy statusflag BIT#2: MUC/MUCX flag BIT#1: Node fail flag BIT#0: PTM fail flag 13to 17: Error number 18 to 20: Smart plate type on this node 21 to 44:Data and command buffer 45 to 50: Series of pertinent information andcommand flags to all nodes such as node environment variables andproduct version

The length of the serial stream for the SPNT network is at least 50 bitslong.

Using readily commercially available protocol stacks (such as Zigbee)embedded in RF chip solutions such as the one found in the EM250 orEM260 RF chips eliminates much of the tedious communication identitymechanisms between nodes.

System Flow Chart

Referring now to FIGS. 30 and 31, when ACMs are plugged into an ACMconnector, the apparatus 10 analyses the ACM so as to limit the amountof ACM types allowed per apparatus 10. For example, only one heat sensorACM (an ACM used to measure temperature) may be plugged per apparatus10. If the user mistakenly plugs two heat sensor ACMs at the same time,the internal apparatus logic will warn the user. Therefore, logicinitialization involves a logic routine, as illustrated in FIG. 31,which performs a series of ACM compliance tests 700. If there arediscrepancies during the compliance tests, all logic is skipped 701 anda visible LED blink code is issued 702 which is indicative of the noncompliant issue.

In the event where no compliance failures are detected, a series ofdriver activations are executed 703 based on the ISB's, MUCX'sinstalled. A “Process one ACM at a time” flag 704 is tested. If thisflag is FALSE, then the “NO” route is executed and several ACM softwaredrivers are fetched 705 and will be used to interface the ACMs in oneoperation at steps 705, 707, 708, 709, 710, 711, 712. Thus each 32 bitserial data stream sent for control registers and each 32 bit serialdata stream sent for data registers at 708, 709 710 and 711 will fulfillcommand and data operations for all 4 ACM ports simultaneously.

If the “Process one ACM at a time” flag 704 is TRUE, then the alternate“YES” route is executed and one ACM driver is fetched and updated. InFIG. 31, while in the first iteration 714, [x] counter will be 1 andtherefore only the first set of 8 bits of each 32 bit serial stream forthe control and the data registers at 718, 719, 720 and 721 will containvalid control and data information which will correspond to the ACMplugged at ACM connector #1 (or Port 1). Therefore, if [x] counterequals 2, then only the second set of 8 bits of each 32 bit serialstream for the control and the data registers at 718, 719 and 720 and721 will contain valid control and data information which willcorrespond to the ACM plugged at ACM connector #2 (or Port 2). At step715 the correct software driver will be fetched which will used tointerface the respective ACM connected to the ACM connector [x].Therefore, steps 716 to 723 will execute the CD88 communicationsstandard and HUS operations according to the ACM connected at ACMconnector [x]. Another way to view this is when the “Process one ACM ata time” flag is TRUE, it will require four operations of 700, 703, 704,714, 715, 716, 717, 718, 719, 720, 721,722, 723, to process all 4 ACMsper IMB since only one ACM is being processed at a time.

In summary, while “Process one ACM at a time” flag 704 is TRUE, anunlimited series of load, unload, read or write commands are executed ina unique order based on the requirement of all the ACMs being serviced.In addition to these commands, the 5 outputs of each control registermay send logic signals in parallel to the load, unload, read or writecommands in order to satisfy certain hardware logic sequences requiredby the ACMs. The same is true for the steps 718, 719, 720 and 721 while“Process one ACM at a time” flag 704 is FALSE, except that in this modeone ACM at a time is being serviced.

Other Embodiments

It will be apparent to persons skilled in the art that a number ofvariations and modifications can be made without departing from thescope of the invention as defined in the claims.

1. A communications control bus, the bus comprising: a) an IMB slaveCPU; b) at least two registers; c) a first three bit data connector forconnecting the at least two registers, the connector permittingtransmission of a three bit data signal between the at least tworegisters; and d) a network interconnecting the at least two registersand the IMB slave CPU.
 2. The bus, according to claim 1, in which the atleast two registers comprise: a) a first control register; and b) afirst data register; e) the network interconnecting the first controlregister and the first data register, the network being configured suchthat in response to a first at least 8 bit data signal being received atthe first control register, a first 3 bit disable command signal istransmitted by the first control register to the first data register. 3.The bus, according to claim 2, the at least two registers furthercomprise: a) a second control register; b) a second data register; c) athird control register; d) a third data register; e) a fourth controlregister; and f) a fourth data register; g) the network being configuredsuch in response to second, third, and fourth at least 8 bit datasignals being received respectively at the second, third and fourthcontrol registers, a second, third and fourth 3 bit disable commandsignal is transmitted to the respective second, third and fourth dataregisters.
 4. The bus, according to claims 2 or 3, in which the networkis configured such in response to fifth, sixth, seventh and eighth atleast 8 bit data signals being received respectively at the first,second, third and fourth control registers, a fifth, sixth, seventh, andeighth 3 bit load command signal is transmitted to the respective first,second, third and fourth data registers so that each data register ispermitted to receive at least 8 bits of data.
 5. The bus, according toclaim 4, in which the network is configured such in response to ninth,tenth, eleventh and twelfth at least 8 bit data signals being receivedrespectively at the first, second, third and fourth control registers, afifth, sixth, seventh and eighth 3 bit disable command signal istransmitted to the respective first, second, third and fourth dataregisters.
 6. The bus, according to claim 5, in which the network isconfigured such in response to a 3 bit unload command signal istransmitted to the respective first, second, third and fourth dataregisters from the respective first, second, third and fourth controlregisters, the at least 8 bits of data stored in the data registers istransmitted to the IMB slave CPU.
 7. The bus, according to claims 2 or3, in which the first control register is paired with the first dataregister; the second control register is paired with the second dataregister; the third control register is paired with the third dataregister; and the fourth control register is paired with the fourth dataregister.
 8. The bus, according to claim 1, in which the at least tworegisters are connected by a 3 bit command signal.
 9. The bus, accordingto claim 3, in which a first 32 bit stream of data is received by thefirst, second, third and fourth control registers.
 10. The bus,according to claim 3, in which a second 32 bit stream of data isreceived by the first, second, third and fourth data registers.
 11. Thebus, according to claim 10, in which the second 32 bit stream of data istransmitted from the fourth data register to the IMB slave CPU.
 12. Thebus, according to claim 2, in which an SL1 signal wire connects the IMBslave CPU to the first control register.
 13. The bus, according to claim2, in which an SL2 signal wire connects the IMB slave CPU to the firstdata register.
 14. The bus, according to claim 3, in which a first clocksignal wire interconnects the first, second, third and fourth controlregisters to the IMB slave CPU.
 15. The bus, according to claim 3, inwhich an enable signal wire interconnects the first, second, third andfourth control registers to the IMB slave CPU.
 16. The bus, according toclaim 3, in which a second clock signal wire connects the first, second,third and fourth data registers to the IMB slave CPU.
 17. The bus,according to claim 3, in which a DQA feedback wire connects the fourthdata register to the IMB slave CPU.
 18. The bus, according to claim 3,in which each control register includes at least one input/output pinand each data register includes at least one input/output pin.
 19. Thebus, according to claim 7, in which at least three wires interconnecteach paired control register and data register.
 20. The bus, accordingto claim 19, in which each control register transmits a 3 bit commandsignal to each data register located adjacent thereto.
 21. The bus,according to claim 1, in which the at least two registers and the firstthree bit data connector comprise a 13 bit bus.
 22. The bus, accordingto claim 21, in which the 13 bit bus includes an eight bitbi-directional data register and five most significant output bits of anadjacent control register.
 23. The bus, according to claim 22, in whichthe first three bit data connector issues a command to the adjacentcontrol register.
 24. The bus, according to claim 7, in which at leastone ACM connector is connected to each pair of control registers anddata registers.
 25. The bus, according to claim 24, includes four ACMconnectors.
 26. The bus, according to claim 24, further comprising a HUSand a MUC.
 27. The bus, according to claim 26, in which each IMBincludes at least four MUCs.
 28. A modular apparatus for controllingmultiple electronic hardware devices, the apparatus comprising: a) atleast one intelligent master base for use with an electrical circuit; b)a first communications control bus, according to claim 1, located in theintelligent master base; and c) at least one adaptable cube moduleconnected to the intelligent master base, the communications control busbeing adapted to allow the number of adaptable cube modules to beincreased in multiples of four.
 29. The apparatus, according to claim28, in which an intelligent slave base is connected to the intelligentmaster base.
 30. The apparatus, according to claim 29, in which a secondcommunications control bus is located in the intelligent slave base. 31.The apparatus, according to claim 28, in which the intelligent masterbase and the adaptable cube module are sized and shaped for location inan electrical box.
 32. The apparatus, according to claim 28, in which asmart plate is connected to the adaptable cube module.
 33. Theapparatus, according to claim 29, in which a smart plate is connected tothe intelligent slave base.
 34. The apparatus, according to claim 28, inwhich a smart plate is connected to the intelligent master base.
 35. Theapparatus, according to claim 28, in which a slim slave base module isconnected to the intelligent master base.
 36. The apparatus, accordingto claim 28, in which a slim slave base module is connected to theintelligent slave base.
 37. The apparatus, according to claim 28, inwhich the intelligent master base comprises: a) an IMB master CPU; b) anIMB slave CPU electrically connected to the IMB master CPU via an I²Cstandard; c) at least two adaptable cube module connectors for receivingthe adaptable cube modules; d) a first HUS bus interconnecting the atleast two adaptable cube module connectors to the IMB slave CPU; e) acircuit for remotely controlling the multiple electronic hardwaredevices, the circuit being connected to the IMB slave CPU; and f) apower supply for powering the circuit, the IMB master CPU, and the IMBslave CPU, the power supply being connected to an electrical wiringnetwork.
 38. The apparatus, according to claim 37, in which the IMBslave CPU is a PIC micro-controller or DSC/DSP processors.
 39. Theapparatus, according to claim 28, in which each adaptable cube moduleconnector is at least a 28 pin header.
 40. The apparatus, according toclaim 37, further includes an RF transceiver chip having a mesh topologystack, the stack communicating information in the format of the SPTNcommunications protocol.
 41. The apparatus, according to claim 29, inwhich the intelligent slave base further comprises: a) an ISB masterCPU; b) at least two adaptable cube module connectors for receiving theadaptable cube modules; c) a second communications control bus locatedin the intelligent slave base; and d) a second HUS bus interconnectingthe at least two adaptable cube module connectors to the ISB master CPU;and e) a power supply for powering the ISB master CPU, the power supplybeing connected to the IMB.
 42. The apparatus, according to claim 28, inwhich each adaptable cube module comprises: a) an adaptable cube moduleconnector for receiving the intelligent master base; b) a conductivecircuit having an eight bit bus portion, and first and second routes; c)an 8 bit bus control buffer connected to the second route; and d) aplurality of resistors connected to the first route, the resistorsdefining an address of the adaptable cube module, the conductive circuitcommunicating data from the intelligent master base to the resistors.43. The apparatus, according to claim 42, includes the adaptable cubemodule connector includes a plurality of connections for use with HUSservices.
 44. The apparatus, according to claim 42, in which theconductive circuit further comprises a buffer latch control connected toan output of a control register.
 45. The apparatus, according to claim42, further comprises a smart plate cover interface.
 46. The apparatus,according to claim 45, in which the smart plate cover interface and theadaptable cube module are one-piece.
 47. The apparatus, according toclaim 42, in which the resistors are parallel pull up or pull downresistors.
 48. The apparatus, according to claim 29, wherein theintelligent slave base and the intelligent master base are connected bya base expansion connector.
 49. The apparatus, according to claim 48, inwhich the base expansion connector comprises an I²C standard.
 50. Theapparatus, according to claim 45, in which the smart plate includes asmoke detector, at least one infra red proximity detector, at least onemotion detector, at least one GFI (Ground fault interruption), at leastone Arc detection, or at least one lighting dimmer circuit.
 51. Theapparatus, according to claim 31, in which the intelligent master baseand the adaptable cube module are located in an 1104, 4×4 or 4/11/16,6×6, 8×8, 10×10, 12×12, 16×16 or 24×24 electrical box.
 52. Theapparatus, according to claim 35, in which the slim slave base modulecomprises a PC board for communicating conductive traces between baseexpansion connectors, the board having located therein a plurality ofholes through which power conductors pass independent of the conductivetraces.
 53. The apparatus, according to claim 35, in which the slimslave base module comprises a PC board for communicating conductivetraces between base expansion connectors, the board having a pluralityof housing terminal screws for connecting to the electrical wiringsystem.
 54. An intelligent master base comprising: a) an IMB master CPU;b) an IMB slave CPU electrically connected to the IMB master CPU via anI²C standard; c) four adaptable cube module connectors for receivingrespectively four adaptable cube modules; d) a HUS bus interconnectingthe adaptable cube module connectors to the IMB slave CPU; e) a circuitfor remotely the controlling the multiple electronic hardware devices,the circuit being connected to the IMB slave CPU; and f) a power supplyfor powering the circuit, the IMB master CPU, and the IMB slave CPU, thepower supply being connected to an electrical wiring network.
 55. Theintelligent master base, according to claim 54, in which the IMB slaveCPU is a PIC micro-controller or DSC/DSP processors.
 56. The intelligentmaster base, according to claim 54, in which each adaptable cube moduleconnector is at least a 28 pin header.
 57. The intelligent master base,according to claim 54, further includes an RF transceiver chip having amesh topology stack, the stack communicating information in the formatof the SPTN communications protocol.
 58. (withdrawn; currently amended)An intelligent slave base comprising: a) an ISB master CPU; b) four cubemodule connectors for receiving respectively four adaptable cubemodules; c) a communications control bus according to claim 1; d) a HUSbus interconnecting the adaptable cube module connectors to the ISBmaster CPU; and e) a power supply for powering the ISB master CPU, thepower supply being connectable to an intelligent master base.
 59. Anadaptable cube module comprising: a) an adaptable cube module connectorfor receiving an intelligent master base; b) a conductive circuit havingan eight bit bus portion, and first and second routes; c) an 8 bit buscontrol buffer connected to the second route; and d) a plurality ofresistors connected to the first route, the resistors defining anaddress of the adaptable cube module, the conductive circuitcommunicating data from the intelligent master base to the resistors.60. The adaptable cube module, according to claim 59, in which theadaptable cube module connector includes a plurality of connections foruse with HUS services.
 61. The adaptable cube module, according to claim59, in which the conductive circuit further comprises a buffer latchcontrol connected to an output of a control register.
 62. The adaptablecube module, according to claim 59, in which the resistors are parallelpull up or pull down resistors.
 63. A slim slave base module comprising:a PC board for communicating conductive traces between base expansionconnectors, the board having located therein a plurality of holesthrough which power conductors pass independent of the conductivetraces.
 64. A slim slave base module comprising a PC board forcommunicating conductive traces between base expansion connectors, theboard having a plurality of housing terminal screws for connecting tothe electrical wiring system.
 65. The apparatus, according to claim 32,in which the smart plate includes features selected from the groupconsisting of: a graphical color touch screen, a battery charger,proximity sensors, a long range motion sensor, a thermostat, a lux meter(TAOS technology, a smoke detector, doorbell buzzer system, video cameraimages, a humidistat an intercom system an intrusion system, a camera,programmable control function blocks, a permanent or/and detachablenightlight, virtual switches/dimmers, telephone and smart taggingsystems, displays readings associated to the establishment's hot watertank(s) which determine the amount of hot water available per tank. 66.The apparatus, according to claim 31, in which the electrical boxincludes any a combination of one or more hardware devices selected fromthe group consisting of: IMB, ISB, MUCX's, RF communications in the IMB,lighting dimmer circuits, connectivity for a graphical color touchscreen, a long range motion detector, thermostat, a lux meter (TAOStechnology), smoke detector, doorbell buzzer button, humidistat,intercom, camera, battery charger, GFI (Ground fault interruption), arcdetector, single or duplex receptacles, motion sensor, single/doublepole button switches, AC/DC discrete low/high voltage input, AC/DCdiscrete low/high voltage output, DC analog voltage/current output, DCanalog voltage/current input, CO₂ sensor, RS232 RF links, DAC, ADC,on/off photocell, RS232, RF-RS-232, RS-422, RS-485, RF-RS-422,RF-RS-485, pulse width modulator output, buzzer, night light, power barwith electrical cord, witch/dimmer buttons and battery charger.
 67. Theapparatus, according to claim 37, in which the intelligent master baseis cuboid.
 68. The apparatus, according to claim 41, in which theintelligent slave base is cuboid.
 69. The apparatus, according to claim42, in which the adaptable cube module is cuboid.
 70. A one-pieceapparatus for controlling multiple electronic hardware devices, theapparatus comprising: a) an adaptable cube module connectable to anintelligent master base; and b) a smart plate cover interface connectedto the adaptable cube module.
 71. The apparatus, according to claim 70,in which the smart plate includes features selected from the groupconsisting of: a graphical color touch screen, a battery charger,proximity sensors, a long range motion sensor, a thermostat, a lux meter(TAOS technology, a smoke detector, doorbell buzzer system, video cameraimages, a humidistat an intercom system an intrusion system, a camera,programmable control function blocks, a permanent or/and detachablenightlight, virtual switches/dimmers, telephone and smart taggingsystems, displays readings associated to the establishment's hot watertank(s) which determine the amount of hot water available per tank. 72.A circuit for remotely controlling multiple hardware devices, thecircuit comprising a communications control bus, according to claim 1.73. A method of remotely controlling multiple electronic hardwaredevices using a communications control bus, the method comprising: a)electrically interconnecting a first control register, a first dataregister, and an IMB slave CPU; and b) transmitting a three bit datadisable signal from the first control register to the first dataregister.
 74. The method, according to claim 73, further comprising: a)receiving a first at least 8 bit data signal at the first controlregister; and b) transmitting a first 3 bit disable signal from thefirst control register to the first data register.
 75. The method,according to claim 74, further comprising: a) receiving second, third,and fourth at least 8 bit data signals at respective second, third andfourth control registers; and b) transmitting a second, third and fourth3 bit disable command signal to the respective second, third and fourthdata registers.
 76. The method, according to claim 75, furthercomprising: a) receiving fifth, sixth, seventh and eighth at least 8 bitdata signals respectively at the first, second, third and fourth controlregisters allowing its previous first, second, third and fourth databytes to be transferred to the fifth, sixth, seventh and eighth controlregisters; and b) transmitting a fifth, sixth, seventh, eighth, ninth,tenth, eleventh and twelfth 3 bit load command signal to the respectivefirst, second, third, fourth, fifth, sixth, seventh and eighth dataregisters so that each data register is permitted to receive at least 8bits of data.
 77. The method, according to claim 76, further comprising:a) receiving ninth, tenth, eleventh and twelfth at least 8 bit datasignals respectively at the first, second, third and fourth controlregisters allowing its previous fifth, sixth, seventh and eighth databytes to be transferred to the fifth, sixth, seventh and eighth controlregisters; and b) transmitting a thirteenth, fourteenth, fifteenthsixteenth, seventeenth, eighteenth, nineteenth and twentieth, 3 bitdisable command signal to the respective first, second, third fourth,fifth, sixth, seventh and eighth data registers.
 78. The method,according to claim 77, further comprising: a) transmitting a 3 bitunload command signal to the respective first, second, third, fourth,fifth, sixth, seventh and eighth data registers from the respectivefirst, second, third, fourth, fifth, sixth, seventh and eighth controlregisters; and b) transmitting the at least 8 bits of data stored in thedata registers to the IMB slave CPU.
 79. A method of controllingmultiple electronic hardware devices using a touchless smart plateinterface having a proximity detector, the smart plate interface beingconnected to a modular apparatus, according to claim 28, the methodcomprising: waving a hand at least once near the proximity detector tocontrol operation of a first electronic hardware device.
 80. The method,according to claim 79 further comprising, after waving the hand at leastonce, pausing the hand near the proximity detector so as to furthercontrol operation of the first electronic hardware device.
 81. Themethod, according to claim 79, in which two consecutive hand wavingsnear the proximity detector operates a second electronic hardwaredevice.
 82. The method, according to claim 81, in which two consecutivehaving wavings followed by a pause near the proximity detector furthercontrols operation of the second hardware device.
 83. The method,according to claim 79, in which three consecutive hand wavings near theproximity detector operates a third electronic hardware device.
 84. Themethod, according to claim 83, in which three consecutive hand wavingsfollowed by a pause near the proximity detector further controls thethird electronic hardware device.
 85. The method, according to claim 79,in which the hand is moved orthogonal to the proximity detector so as tofurther control the electronic device.
 86. The method, according toclaim 85, in which the hand is moved orthogonal to the proximitydetector so as to dim lights.